The described embodiments relate generally to power conversion. More particularly, the described embodiments relate to systems, methods and apparatuses to reduce high-frequency noise during operation in pulse-skipping mode.
A switched DC-DC converter may be constructed from a set of switches and energy storage elements (inductors and capacitors). A simplified example of a buck converter 101 is given in
In PWM operation with a constant clock frequency, the state of the switches is changed every clock. The change in switch state is typically accomplished by charging and discharging the capacitance of a transistor gate; in non-resonant implementations, the charge removed from the gate is then sent to ground and lost. Thus, there is a driver power consumption of at least CgateVgate2fSW to operate each switch in PWM mode, where Cgate is the gate capacitance of the switch, Vgate the change in voltage needed to change the switch from the OFF state to the ON state, and fSW is the switching frequency. Typically the requirement for a driver circuit to provide the control signals to the switching transistors increases overall power consumption by a factor of 1.5 to 2. In addition, switching losses within the transistor occur at each switching transition where both the current and the voltage across the transistor during switching are non-zero. Thus, substantial power is required to operate in PWM mode. When the load power is small, the efficiency of the DC-DC conversion process may be very poor, particularly if a high switching frequency is employed to ensure rapid control response at high load conditions.
To improve light-load efficiency, it is well-known to provide a lower-power mode in which the switches spend much of the time in a fixed state (typically both off). Reduced power operation is variously known as pulse-frequency mode, pulse-skipping mode, discontinuous mode, and so on, depending on the exact approach used to control the converter in this mode. For example, a pulse-skipping mode (PSM) may be employed in which the converter produces bursts of switching pulses at a fixed frequency, followed by periods in which no switching takes place. An idealized example of this type of operation is depicted in
During the burst time, as shown by trace 320, the output voltage will rise as desired if the duty cycle is chosen to be higher than that required to provide the output voltage at the start of the burst. For example, during PSM operation, the duty cycle controller may receive feedback from an emulated “replica” converter, consisting of small switches and an output filter, instead of from the actual output. By imposing a target output voltage slightly higher than the actual voltage, e.g. Dtarget=DfVout/Vin where the duty factor Df>1, the duty cycle rises to a higher value than required to maintain the nominal output voltage Vout. The width of the voltage variation, δVh, is selected to meet the requirements of a given application. Various alternative means, such as insertion of a series offset voltage onto the reference voltage Vref, or the sensed voltage Vsense, may also be used.
In a real converter (such as, converter 401), the output capacitor has an associated equivalent series resistance ESR and equivalent series inductance ESL, depicted schematically in
The presence of finite ESL and ESR result in undesired high-frequency components in the output voltage. The output voltage variation due to ESL is substantially at the switching frequency and higher harmonics. By judicious selection of switching frequency, as described for example in U.S. Pat. No. 8,145,149, any resulting spurious output of a power amplifier driven by the converter may be minimized in the specific channels and bands of interest. However, the effect of an ESR-related sudden change in output voltage is to produce a broad output spectrum, which may contain power at inconvenient frequency ranges. When the converter is used to drive a radio-frequency power amplifier, the presence of high-frequency harmonics in the supply voltage from the converter may cause increased error-vector magnitude (EVM) when inside the transmitted channel, and increased adjacent-channel power ratio (ACPR) when outside the transmitted channel.
Methods of shaping PSM pulses in lower-switching-frequency converters to reduce the analogous audible harmonic content have been reported. Some methods employ linearly-increasing peak current with each switching pulse during a burst. These methods are intended for audible noise coupling due to magnetostriction, and are not helpful in reducing ESR-related harmonics from the termination of the pulse. For high-frequency converters, with switching frequency of 10 MHz and above, it is difficult to sense peak current rapidly enough to employ current-mode control, and thus voltage-mode control is preferred.
Some methods include the placement of one or more shortened (reduced-duty-cycle) pulses at the beginning and end of a PSM burst, used to minimize current peaks as well as reduce audible noise. These methods are applicable to harmonic reduction, but adjustment of individual pulse durations may be challenging to implement in a high-frequency converter. Therefore it is useful to employ an alternative method of reducing harmonic content due to output ESR.
An embodiment includes a voltage regulator. The voltage regulator includes a series switch element connected between a first voltage supply and a common node, wherein the series switch element comprises a plurality of partitioned series switch elements, a shunt switch element connected between a second voltage supply and the common node, and a switching controller that controls closing and opening of the series switch element and the shunt switch element, generating a switching voltage at the common node. The switching controller is operative to control the series switch element and the shunt switch element in an idle state, wherein none of the plurality of partitioned series switch elements are active, control the series switch element and the shunt switch element in a burst state, wherein N of the plurality of partitioned series switch elements are active, and control the series switch element and the shunt switch element in a transition state, wherein M of the plurality of partitioned series switch elements are active, and wherein M is less than N.
Another embodiment includes a voltage regulator. The voltage regulator includes a series switch element connected between a first voltage supply and a common node, wherein the series switch element comprises a plurality of partitioned series switch elements, a shunt switch element connected between a second voltage supply and the common node, a switching controller that controls closing and opening of the series switch element and the shunt switch element, generating a switching voltage at the common node. The switching controller is operative to control the series switch element and the shunt switch element in an idle state, wherein none of the plurality of partitioned series switch elements are active, and wherein a series resistance of series switch element is a value Roff, control the series switch element and the shunt switch element in a burst state, wherein a series resistance of the series switch element is a value Ron, and control the series switch element and the shunt switch element in a transition state, wherein a series resistance of the series switch element is a value Ron1, wherein Ron1 is greater than Ron, and Ron1 is less than Roff.
Another embodiment includes a voltage regulator. The voltage regulator includes a series switch element connected between a first voltage supply and a common node, a shunt switch element connected between a second voltage supply and the common node, wherein the shunt switch element comprises a plurality of partitioned shunt switch elements, and a switching controller that controls closing and opening of the series switch element and the shunt switch element, generating a switching voltage at the common node. The switching controller is operative to control the series switch element and the shunt switch element in an idle state, wherein none of the plurality of partitioned shunt switch elements are active, control the series switch element and the shunt switch element in a burst state, wherein L of the plurality of partitioned shunt switch elements are active, and control the series switch element and the shunt switch element in a transition state, wherein K of the plurality of partitioned shunt switch elements are active, and wherein K is less than L.
Another embodiment includes a method of generating a regulated voltage. The method includes generating the regulated voltage through controlled closing and opening of a series switch element and a shunt switch element, the series switch element being connected between a first voltage supply and a common node, and the shunt switch being connected between the common node and a second supply voltage, wherein the series switch element comprises a plurality of partitioned series switch elements. The controlled closing and opening of a series switch element and a shunt switch element includes an idle state, wherein none of the plurality of partitioned series switch elements are active, a burst state, wherein N of the plurality of partitioned series switch elements are active, and a transition state, wherein M of the plurality of partitioned series switch elements are active, and wherein M is less than N.
The described embodiments include partitioning of one or more switch elements of a voltage regulator. The partitions of the switch elements are selectively activated to reduce harmonic content due to output equivalent series resistance ESR.
An example of a measured burst output voltage is depicted in
The resulting abrupt step produces an increase in broadband noise in the converter output. Analytic estimates of the power spectrum for an idealized PSM triangle wave, shown in inset 610, and a triangle wave with an abrupt step, shown in inset 620, are depicted in
In an embodiment, at least the series switch SW1 is partitioned into a plurality of segments, each of which may participate in switching (active) or remain in an inactive condition in which that segment remains open when other segments alternate between open and closed (idle); the shunt switch SW2 may also be partitioned in a similar fashion.
A partitioned switch of this type is described in U.S. Pat. No. 8,233,250, and a simplified example is depicted schematically in
For at least some embodiments, the switching controller 730 is operative to control the series switch element 710 and the shunt switch element 712 in an idle state, wherein none of the plurality of partitioned series switch elements s1-0, s1-1, s1-2, s1-3 are active. Further, the switching controller 730 is operative to control the series switch element 710 and the shunt switch element 712 in a burst state, wherein N of the plurality of partitioned series switch elements s1-0, s1-1, s1-2, s1-3 are active. Further, the switching controller 730 is operative to control the series switch element and the shunt switch element in a transition state, wherein M of the plurality of partitioned series switch elements are active, and wherein M is less than N. For the described embodiments, the active partitioned series switch elements are controllable for closing and opening of the series switch element. An output voltage (VOUT) is generated at a load (Rload) of the voltage regulator.
For at least some embodiments, the switching controller 730 is operative to transition the voltage regulator from the idle state to the burst state when the output voltage (VOUT) is less than a VMIN threshold. For at least some embodiments, the switching controller 730 is operative to transition from the burst state to the transition state when the output voltage (VOUT) is greater than a VMAX threshold. For at least some embodiments, the switching controller 730 is operative to transition from the transition state to the idle state after a predetermined number of switching cycles. For at least some embodiments, the switching controller 730 is operative to transition from the transition state to the idle state after a predetermined amount of time.
For at least some embodiments, the transition state includes a plurality of stages (wherein a stage is a portion of time of the transition state), wherein each stages includes the selection of a different number of partitioned series switch elements that are active. For an embodiment, the different number of partitioned series switch elements that are active decreases in time between the burst state and the idle state.
For at least some embodiments, a duty cycle of the closing and opening of the series switch element and the shunt switch element (basically, the switching voltage VSW) decreases during the transition state. Further, for at least some embodiments, the duty cycle of the closing and opening of the series switch element and the shunt switch element decreases for each of the plurality of stages of the transition state.
For at least some embodiments, the shunt switch element includes a plurality of partitioned shunt switch elements, wherein none of the plurality of partitioned shunt switch elements are active during the idle state, and wherein L of the plurality of partitioned shunt switch elements are active during the burst state, and wherein K of the plurality of partitioned series switch elements are active during the transition state, and wherein K is less than L. That is, the number of active partitioned shunt switch elements is less during the transition state than during the burst state.
When a large number of segments is active, substantial driver power is used changing the switch state, but series parasitic resistance Rpar,sw in the ON state is minimized. As the number of active segments is reduced, the series resistance of the overall switch increases. When the switches are operated at a duty cycle higher than that corresponding to the current output voltage, the average output current rises over times of order (Lout/Rpar) to approximately
where the total parasitic resistance Rpar is the sum of that due to the switch segments Rpar,sw and the equivalent series resistance of the inductor Rpar,ind. (The capacitor ESR is also present, but is usually small compared to Rpar,ind.) It is expected that the resistance of n substantially identical segments in parallel will be reduced by roughly 1/n compared to the resistance of a single segment. The number of segments made active at a given time can be used to adjust the parasitic resistance of the overall switch; when a small number of segments are in use, the resistance is increased, and the peak charging current reduced. Thus, charging current, and consequently the effect of capacitor ESR on output voltage, can be reduced by decreasing the number of active segments.
An exemplary embodiment is summarized in
When the output voltage of the converter falls below the hysteresis threshold, the switches must become active again to recharge the output capacitance (step 930). The converter must operate at a duty cycle sufficiently high to charge the output capacitance, but not so high as to produce excessive inductor current. An exemplary method for achieving this end multiplies the ratio of target output voltage to input voltage by a D-factor Df>1, to produce a duty cycle D corresponding to an increased nominal output voltage. The value of Df is adjusted for a given converter and application. Various alternative means, such as the addition of a fixed voltage to the reference input, may also be employed. A fixed number of segments of SW1, Nseg,burst, is active during steps 930 and 940. The value of Nseg,burst is selected to optimize efficiency and charging time. SW2 may also be segmented, and a subset or all of the available segments employed, during step 930, as needed to optimize efficiency.
During the active period, the output voltage is compared against the upper hysteresis threshold (VMAX) (step 940). When the output voltage reaches the upper hysteresis threshold, the first stage of the burst transition is initiated. The Stage parameter is set to 1 (step 950), and the number of active segments is reduced (step 960). In the exemplary embodiment, the number of segments is reduced by a factor of 2 for each new stage, but other approaches, such as a linear decrease in the number of active segments in each stage, may also be used. The switches continue in the active state for a fixed integer number of switching cycles, here denoted m (step 970). Note that the value of m may depend on the parameter Stage. A fixed time may also be used. If Stage is not yet equal to the maximum desired value Maxphase (step 980), the number of active segments is again reduced and another m switching cycles, or equivalent, are performed. If Stage=Maxphase, the switches are returned to the idle state (step 910), and the output voltage is allowed to discharge again until the lower hysteresis threshold (VMIN) is reached, or PSM operation terminates.
In an alternative embodiment, segment reduction may be combined with changes in duty cycle, through modification of the duty factor Df. An example embodiment is depicted in
It may also be desirable to change the response time of the means used to control duty cycle during the transition state procedure (steps 1050-1080) to allow the actual duty cycle of SW1 and SW2 to rapidly adjust to the requested value in each stage. In the embodiment of
Although the described embodiments employ activation of segments of a switch partitioned therein, other means of adjusting switch parasitic on-resistance may also be employed. For example, when an MOS transistor is used as the switch, the resistance of the transistor can be adjusted by changing the gate voltage applied during the transistor is turned on. For an n-channel (NMOS) device with small drain voltage,
where Ron=Rpar,sw is the low-field resistance, μeff is the effective carrier mobility, W the device width, L the gate length, Vg the gate voltage, Vth the threshold voltage, and VD the drain voltage. Analogous considerations apply for PMOS transistors, or MESFET devices. By changing the gate voltage instead of, or in addition to, the number of active segments, during each stage of operation as described in
A simulated example of the results of the described embodiments is depicted in
It is apparent from trace 1220 that the large step at the end of charging has been eliminated, and a small step of about 13 mV remains when stage 3 end (step 1080).
The measured output spectra of a power amplifier, carrying a modulated wideband CDMA (WCDMA) signal, driven by the converter of
Although specific embodiments have been described and illustrated, the embodiments are not to be limited to the specific forms or arrangements of parts so described and illustrated.
This patent application claims priority to U.S. Provisional Patent Application 61/773,884, filed Mar. 7, 2013, which is herein incorporated by reference.
Number | Date | Country | |
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61773884 | Mar 2013 | US |