Patent Application
20130065546
Filters are commonly used components in many different circuit types. In the context of radios, filters are used to remove noise from signals being processed in different frequency domains. For example, in receivers that convert an incoming RF signal to an intermediate or low intermediate frequency signal, a DC component output by a mixer might disturb the reception and can be filtered out by a DC filter to improve receiver performance such as receive sensitivity. This DC filter usually has a very low corner frequency such that its filtering has a minimum effect on the desired received signal. The lower the corner frequency however, the more time it takes for the filter to settle after the receiver is enabled. This extended settling duration adds to the power consumption and to a transmit-to-receive turnaround time in cases where the receiver is combined with a transmit function.
According to one aspect, the present invention includes a receiver having a signal processing path to receive and process an incoming radio frequency (RF) signal to obtain a demodulated signal. This path can include one or more filters, where a filter state of at least one filter can be stored and restored to enable a faster re-settling time. To this end, the receiver may include a quality detector to detect a quality level of the demodulated signal and output a quality indicator based on at least one of the quality level of the demodulated signal, a quality metric of the incoming RF signal, and a quality metric of a signal being processed in the signal processing path. In turn, a controller coupled to the filter may cause a state of the filter to be stored in a memory responsive to the quality indicator, and cause the stored state to be restored to the filter when the receiver is re-enabled from a low power state.
As one example, a filter can include a first amplifier to receive the downconverted signal, where the first amplifier has a first programmable amplification value and outputs a first amplifier value, and a second amplifier to receive a delay cell output, where the second amplifier has a second programmable amplification value and outputs a second amplifier value. In turn, a combiner of the filter can sum the first and second amplifier values to generate a filter estimate, and a second combiner can remove the filter estimate from the downconverted signal to output a filtered signal.
Another aspect of the present invention is directed to a method that includes receiving and processing an incoming RF signal in a receiver to obtain a demodulated signal, allowing a filter in a signal processing path of the receiver to settle, and storing a filter state of the filter in a storage area responsive to a signal quality metric of the demodulated signal being at least at a threshold level. Thereafter, this stored filter state can be obtained from the storage area and provided to the filter when re-enabling the receiver. As examples, the signal quality metric can be at least one of a preamble detection, a synchronization word detection, a valid checksum computation, and a received signal strength indicator.
A still further aspect of the present invention is directed to a system that includes a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, a mixer to receive and downconvert the RF signal to a second frequency signal, a filter to receive and filter the second frequency signal, a demodulator to receive and demodulate the filtered second frequency signal to output demodulated data, and a quality detector to detect a quality of the demodulated data and output a quality indicator based on the data quality. In addition, the system can include a controller coupled to the filter to cause a state of the filter to be stored into a storage responsive to the quality indicator. By storage of this state and the later restoring of the state back to the filter, the filter, which may be a DC filter, can re-settle within a first time period that is substantially less than a second time period at which the filter settles without the stored state.
In various embodiments, a state of a filter can be maintained in a storage mechanism when it is determined that an appropriate level of quality with regard to a filtered signal has been achieved. By way of this state storage, embodiments may enable improved performance and power consumption. Specifically, by storing one or more state values of a filter present in a receiver, a reduced settling time can be achieved upon a re-settling of the filter on a different enabling of the receiver, by initializing the filter with this saved value. Furthermore, because of this reduced settling time, power consumption can be reduced. That is, assume that a receiver periodically awakens to detect the presence of signals directed to it. By way of a faster settling, the presence or absence of incoming signals for the receiver can be determined more quickly and accordingly the receiver can more rapidly return to a low power mode when it is determined that no signals are being directed to it. Although described herein in the context of a receiver, which may be a standalone receiver or part of a transceiver, persons of ordinary skill in the art understand that the scope of the present invention is not limited in this regard and in various embodiments filter state storage as described herein can be applied to other environments in which a filter is used. For example, such state storage can be used in sensor devices using e.g., a low duty cycle mode. Also devices that use some form of successive approximation (or binary search) may benefit such that the range of the successive approximation can be adjusted based on a previous measurement, saving active time and hence power consumption.
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The filtered output from filter 140 in turn is provided to a DC filter 150, which may provide DC filtering to thus remove DC offsets that may be present in the incoming signal. This filter may thus remove any DC offset in the RF mixer stage and subsequent circuitry such as the PGA. In the context of a LIF or ZIF receiver, the received signal spectrum is overlapping or closely positioned relative to the DC offset component. As a demodulation process is predicated on a certain signal-to-noise ratio (SNR) to reliably receive a desired signal, the DC offset can be removed to avoid reduction in SNR. As will be described further below, in some embodiments DC filter 150 can be implemented using a recursive filter.
Furthermore, in accordance with an embodiment of the present invention, state information from DC filter 150 can be obtained and stored at an appropriate point during the signal processing to enable a more rapid settling of the DC filter (and thus receiver) on another enabling of the receiver. As seen, DC filter 150 may be coupled to a controller 170. As an example, controller 170 may be a microcontroller unit (MCU) of the receiver. Furthermore as seen, controller 170 can include a storage 175 in which the filter state can be stored. However, persons of ordinary skill in the art understand that the location of the state storage within other locations of the receiver than within in the controller.
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From this analysis performed in quality detector 165, a quality indicator may be communicated to controller 170 when a given quality level of the demodulated signal and/or a quality metric with respect to the RF signal and a signal being processed in the receiver has been attained. For example, the quality indicator can be sent when at least one of the receiver quality metrics exceeds a threshold level, or a given data was correctly received. In various embodiments, this quality indicator may be used by controller 170 to cause a storage of the filter state from filter 150. Thus as seen in
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Furthermore, to realize quick re-settling of DC filter 150 embodiments may, upon powering up of a system including the receiver, provide the stored state to delay cell 156 and beginning re-settling of the filter. This DC estimate may be used to thus enable rapid re-settling. While shown with this particular implementation in the embodiment of
Note that an initial settling of filter 150 can consume many samples of an incoming signal. However, using a stored state of the filter for a re-settling, many fewer samples can be used to re-settle the filter. Thus re-settling can consume a substantially smaller time period than an original settling. As one example when the DC filter is used in an IF portion of a receive signal processing path of a short range radio, an initial settling can consume between approximately 200 and 400 samples, while for a re-settling much fewer samples, e.g., between approximately 0 and 20 samples may be consumed.
The settling time can depend upon the speed of the filter, which can be controlled by appropriate values of the coefficients of amplifiers 154 and 158. This setting time may also depend on DC suppression. In general direct conversion receivers implement more DC suppression than low IF receivers because a low IF receiver may provide some filtering of the DC component. In one embodiment, coefficient α used for amplifier 154 may be set equal to 1-β, where β is the coefficient used for second amplifier 158, and which may be set in this embodiment between 0 and 1. By setting β relatively low, a higher alpha value is provided and thus the feedback mechanism is relatively slow, causing a longer settling time and better suppression of the DC component. Instead when a faster feedback mechanism is provided by implementing a greater beta value, a faster settling time may be realized, albeit with a higher filter cutoff frequency. The higher cutoff frequency may filter out a part of the received signal spectrum, which sets a limit on the settling time.
With regard to a particular implementation of a receiver, it can be assumed that the DC offset may be a relatively low value, e.g., between approximately 0.05% and 0.1%, due to a CMOS receiver design having good matching that seeks to avoid nonlinearities and minimize DC offset. Assume in this case that an expected level of the input signal can be approximately 1V. With an expected DC offset of 0.1%, the DC offset may correspond to approximately 1 mV of offset. On an initial settling time when the filter state starts at zero (e.g., no value is stored in the delay cell), a large number of samples may be processed within the receiver signal processing path including the filter before an appropriate DC estimate is obtained. Assume that at the completion of settling of the DC filter, the DC estimate substantially corresponds to the actual DC offset. Accordingly, this DC estimate can then be stored in a storage of the receiver so that upon a later re-powering of the receiver and re-settling of the filter, a much more rapid settling can occur by restoring this stored DC estimate into the filter prior to initiation of re-settling.
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When at diamond 240 it is determined that the one or more signal quality metrics have been met, control passes to block 250 where the filter state can be stored in a storage area. The storage area can be RAM or other storage within the receiver, in various embodiments. Thus because the filter has settled, incoming RF signals can be received and processed (block 260). Accordingly, demodulated signals at this point may be of a desired quality and can be provided to an end user, e.g., as output demodulated audio signals or to another location when the signals are a communication of data information.
At block 270, processing of the incoming RF signals can be completed and accordingly the receiver can be disabled, e.g., to reduce power consumption. For example, assume the context of a portable device used for packet-based short range wireless communications of data. In this context, a receiver may be powered up temporarily to determine whether any RF signals are directed to the receiver. If not, the receiver can be placed back into a low power mode and disabled. For example, the radio can be configured to periodically be enabled to detect whether any packets are received. If there is no preamble detected, the receiver can be rapidly disabled. Instead, upon a valid preamble detection, the receiver can remain on to obtain a full packet or at least a portion thereof to determine whether the packet is directed to the receiver. If so, the radio can remain on for a longer time period to receive the full packet. Otherwise, it can be powered off.
Still with reference to
Although shown with this high level operation in the embodiment of
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From the disabled state, the receiver can again be re-enabled responsive to an active receive enable signal. At this time, the controller can generate a restore signal (Restore_VDC) to provide the previously stored state value to the filter. Accordingly, the filter may rapidly settle, as this stored state value may be very close to the actual state value. Note that as time proceeds, the quality indicator can be activated as appropriate, which in turn causes a new state of the filter to be stored responsive to the store state signal. In this way, it is possible for a more accurate state value to be provided on re-enabling of the receiver. Although shown with these particular signals in the embodiment of
Referring now to
In a transmit direction, data to be transmitted may be provided from application processor 690 via a serial data port, which is coupled to a modulator/demodulator 680. The modulated information can be provided to a phase lock loop (PLL) 615, which provides the modulated signal to a voltage control oscillator (VCO) 620 where it is upconverted to a RF frequency. As seen, PLL 615 may be fractional-N PLL including a phase frequency detector 612, coupled to receive a reference frequency via an oscillator 605, a charge pump 614, a low pass filter 616, and an N divider 618.
The resulting RF signal is provided to a VGA 625 to provide a variable gain to the RF signal. As seen, multiple fixed gain stages 630a-630n may be coupled between VGA 625 and a power amplifier 635, which outputs an amplified signal through an antenna switch 650 to antenna 655.
In a receive direction, incoming RF signals may be coupled through switch 650 to a receive path including a low noise amplifier (LNA) 660, which provides an amplified output to a mixer 665, which downmixes the signal according to an LO frequency which may be received, in one embodiment from VCO 620.
The downmixed signal, which may be at a low IF or zero IF frequency, is provided through a PGA 668, a DC filter 669, a VGA 670 and an analog-to-digital converter (ADC) 675, which provides a digital bit stream to demodulator 680, which demodulates the information and communicates it to application processor 690.
As further seen, a controller 640 such as a microcontroller unit (MCU) may be coupled to filter 669 to control the storing of filter state information into a memory 674, which in the embodiment of
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
