Patent Application
20060133135
This invention relates generally to electronic circuits. More particularly, this invention relates to reducing power in SRAMs.
As more electronic circuits are included on a single die, the power dissipated by a single die continues to increase. The power consumption causes the die temperature to increase, degrading the circuits' performance and reliability. In order to keep a single IC (integrated circuit) at a reasonable temperature, many techniques have been used to cool the IC. For example, elaborate cooling fins have been attached to the substrate of ICs. Also, fans have been positioned near a group of IC's to cool them. In some cases, flowing liquids have been used to remove the heat produced by ICs. These solutions can be costly and may require a great deal of space, where space is at a premium. If the power on ICs can be reduced while still achieving higher levels of integration, the cost and volume of a product that use ICs may be reduced.
The number of bits contained on chips containing SRAM, has, on average, quadrupled every three years. As a result, the power that the SRAM consumes has increased. Computer systems can use large numbers of stand-alone SRAM or logic chips with large quantities of embedded SRAM and as a consequence, the power consumed by computer systems, on average, has increased. As the number of SRAM bits on a chip has increased, the voltage applied to these chips has been lowered. Lowering the voltage on a chip containing large quantities of SRAM is one method used to lower the overall system power consumption.
Lowering the voltage applied to SRAM may also degrade the stability of a memory cell. As the stability of a memory cell is degraded, the probability of getting incorrect data from a SRAM memory cell increases. An embodiment of this invention lowers the voltage on all circuits except the voltage on memory cells to decrease the overall power used. The memory cells have a higher voltage than the other circuits on the SRAM chip to maintain the stability of the memory cells.
The drain, 108, of NFET, MN3, 120 is connected to the drain of PFET (P-type Field Effect Transistor), MP1, 112, the drain of NFET, MN1, 116, the gate of PFET, MP2, 114, and the gate of NFET, MN2, 118.
The drain, 110, of NFET, MN4, 122 is connected to the drain of PFET (P-type Field Effect Transistor), MP2, 114, the drain of NFET, MN2, 118, the gate of PFET, MP1, 112, and the gate of NFET, MN1, 116.
Data may be read from an embodiment of an SRAM cell shown in
The sizes of NFET, MN1, 116, NFET MN2, 118, NFET MN3, 120, NFET MN4, 122, PFET MP1, 112, and PFET MP2, 114, among other reasons, are chosen to provide enough drive strength to hold the drains of NFETs MN3, 120, and MN4, 122 in their present state preventing the SRAM cell, 124, from flipping when data is read. In addition, the sizes of these six FETs are chosen to simultaneously optimize for the read access time of the SRAM cell, 124.
Data may be written to an embodiment of an SRAM cell shown in
The power supply voltage, VDD, used in this example for the SRAM cell, 124, is the same power supply voltage, VDD, used for all the peripheral circuitry on the SRAM.
The drain, 208, of NFET, MN3, 220 is connected to the drain of PFET (P-type Field Effect Transistor), MP1, 212, the drain of NFET, MN1, 216, the gate of PFET, MP2, 214, and the gate of NFET, MN2, 218.
The drain, 210, of NFET, MN4, 222 is connected to the drain of PFET (P-type Field Effect Transistor), MP2, 214, the drain of NFET, MN2, 218, the gate of PFET, MP1, 212, and the gate of NFET, MN1, 216.
Data may be read from an embodiment of an SRAM cell shown in
The sizes of NFET, MN1, 216, NFET MN2, 218, NFET MN3, 220, NFET MN4, 222, PFET MP1, 212, and PFET MP2, 214, among other reasons, are chosen to provide enough drive strength to hold the drains of NFETs MN3, 220, and MN4, 222 in their present state preventing the SRAM cell, 224, from flipping when data is read. In addition, the sizes of these six FETs are chosen to simultaneously optimize for the read access time of the SRAM cell, 224.
Data may be written to an embodiment of an SRAM cell shown in
The power supply voltage, VCACHE, used in this example for the SRAM cell, 224, is higher than the power supply voltage, VDD, used for all the peripheral circuitry on the SRAM. The voltage provided to the wordline, WL1, 204, must be high enough to ensure that the SRAM cell, 224, can be read and written. The voltage provided to the bitlines, BL1, 200, and BL2, 202, must be high enough to ensure that the SRAM cell, 224, can remain stable when read, and be read and written at speeds required by the circuit.
In this example, because the peripheral circuitry has a lower power supply voltage, VDD, than the power supply voltage for the SRAM cells, VCACHE, power can be saved. At the same time, since the power supply voltage, VCACHE, has a higher voltage than the peripheral circuitry power supply, VDD, the stability and performance of the SRAM cell, 224, is improved.
Other circuitry, 304, including column selects, bitline prechargers, sense amps, and write circuitry, is connected to VDD. Bitline prechargers charge bitline pairs, BL1-BL1N through BL128-BL128N. The bitline pairs, BL1-BL1N through BL128-BL128N, should be charged to a high enough voltage that allows the SRAM cells, 224, to be stable when read.
The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.
