REDUCTION OF THE TIME FOR EXECUTING AN EXTERNALLY COMMANDED TRANSFER OF DATA IN AN INTEGRATED DEVICE

Abstract

Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a generic integrated circuit with input and output data transfer structures according to the prior art.

FIGS. 2A and 2B show physical details of input and output decoupling and driving structures according to the prior art.

FIGS. 3A and 3B illustrate different cumulative delay contributions in inputting and outputting data according to the prior art.

FIG. 4 illustrates a typical ISD protection and decoupling of an externally applied signal and relative effects on the speed of transitions according to the prior art.

FIGS. 5A and 5B illustrate the I/O buffering architecture according of the present invention.

Claims

1-4. (canceled)

5. A method of reducing time for executing a transfer of data in an integrated device controlled by an external device, the method comprising: distributing at least one external signal unbuffered through a distributing line of the integrated device; andlocally realizing a decoupling input buffer for each respective data transfer circuit of the integrated circuit to locally produce a buffered replica of the at least one external signal.

6. The method of claim 5, wherein the integrated device comprises at least one input pad connected to the distributing line and having an allowed input pad capacitance associated therewith, and wherein the distributing line has a width corresponding to the allowed input pad capacitance.

7. The method of claim 5, wherein the at least one externally generated signal comprises at least one of a synchronizing signal and an enabling signal.

8. The method of claim 5, wherein the integrated device comprises a nonvolatile flash memory device, wherein each data transfer circuit comprises a flip-flop and an output data buffer coupled thereto, and wherein the at least one externally generated signal comprises a clock signal and an enabling signal respectively applied to a clock input node of the flip-flop and to an enabling input node of the output data buffer.

9. An input buffering and distributing structure for at least one externally generated signal applied to at least one input pad of an integrated device to be distributed to a plurality of data transfer circuits of the integrated device, the structure comprising: a distributing line connected to the at least one input pad for distributing the at least one external signal unbuffered; anda plurality of decoupling input buffers, each decoupling input buffer locally producing a buffered replica of the at least one externally generated signal for each respective data transfer circuit.

10. The structure of claim 9, wherein the at least one externally generated signal comprises at least one of a synchronizing signal and an enabling signal for the plurality of data transfer circuits.

11. The structure of claim 9, wherein the integrated device comprises a nonvolatile flash memory device, wherein each data transfer circuit comprises a flip-flop and an output data buffer coupled thereto, and wherein the at least one externally generated signal comprises a clock signal and an enabling signal respectively applied to a clock input node of the flip-flop and to an enabling input node of the output data buffer.

12. The structure of claim 9, wherein the at least one input pad has an allowed input pad capacitance associated therewith, and wherein said distributing line has a width corresponding to the allowed input pad capacitance.

13. An integrated device comprising: at least one input pad for receiving at least one externally generated signal;a distributing line connected to said at least one input pad for distributing the at least one externally generated signal unbuffered;a plurality of decoupling input buffers connected to said distributing line;a plurality of data transfer circuits connected to said plurality of decoupling input buffers; andeach decoupling input buffer locally producing a buffered replica of the at least one externally generated signal for each respective data transfer circuit.

14. The integrated device of claim 13, wherein the at least one externally generated signal comprises a synchronizing signal and an enabling signal for said plurality of data transfer circuits.

15. The integrated device of claim 13, wherein the integrated device comprises a nonvolatile flash memory device, wherein each data transfer circuit comprises a flip-flop and an output data buffer coupled thereto, and wherein the at least one externally generated signal comprises a clock signal and an enabling signal respectively applied to a clock input node of said flip-flop and to an enabling input node of said output data buffer.

16. The integrated device of claim 13, wherein said at least one input pad has an allowed input pad capacitance associated therewith, and wherein said distributing line has a width corresponding to the allowed input pad capacitance.

17. An integrated device comprising: at least one input pad for receiving at least one externally generated signal;a distributing line connected to said at least one input pad for distributing the at least one externally generated signal unbuffered;a plurality of decoupling input buffers connected to said distributing line;a plurality of data transfer circuits connected to said plurality of decoupling input buffers, each data transfer circuit comprising an output data buffer coupled thereto; andeach decoupling input buffer locally producing a buffered replica of the at least one externally generated signal for each respective output data buffer.

18. The integrated device of claim 17, wherein the at least one externally generated signal comprises a cock signal.

19. The integrated device of claim 17, wherein the at least one externally generated signal comprises an enabling signal.

20. The integrated device of claim 17, wherein the integrated device comprises a memory device, wherein each data transfer circuit further comprises a flip-flop connected to said output data buffer, and wherein the at least one externally generated signal comprises a clock signal and an enabling signal respectively applied to a clock input node of said flip-flop and to an enabling input node of said output data buffer.

21. The integrated device of claim 17, wherein said at least one input pad has an allowed input pad capacitance associated therewith, and wherein said distributing line has a width corresponding to the allowed input pad capacitance.