Reed-solomon coding device and method thereof

Abstract

To provide a type of Reed-Solomon coding device that allows a reduction of the size and price of the device. When the coding of the Galois field GFb(2m) is performed, in the input-side transformation circuit 116b, the Galois field of the input data is transformed from GFb(2m) into GFa(2m). In RS coding/decoding core unit 112, an operation is then performed on Galois field GFa(2m) to generate the coding data. In output-side transformation circuit 119b, the coding data are transformed from GFa(2m) into GFb(2m). In RS coding/decoding core unit 112, a multiplier corresponding to Galois field GFa(2m) is set.

Description

FIELD OF THE INVENTION

This invention pertains to a Reed-Solomon coding and decoding device, as well as a method for use as the error correction code of recording media and digital transmission.

BACKGROUND OF THE INVENTION

The Reed-Solomon code (referred to as RS code hereinafter) has a high coding efficiency and good performance against burst error. Consequently, it is mainly used as the outer code of recording media and in digital transmission. Also, with the progress in IC technology, it becomes possible to realize coding/decoding IC on a single chip for handling codes with a relatively high correction power for 8-byte correction or higher, and the application range expands rapidly.

The RS code is characterized by the fact that the freedom is very high with respect to the construction method of coding. For example, for the Galois field GF(2 8 ) used frequently in the RS code, usually, the period may be 2 8 −1 as a condition of the field generation polynomial, and hence various types exist. In addition, there is a very wide range of selection of the root of the code generation polynomial that realizes the same correction power. That is, supposing that the root of the field generation polynomial is α, for the condition for realizing correction of the t-byte, as the root of the code generation polynomial, a group of at least 2t consecutive powers of α, that is, {α b , α b+1 , α b+2 , . . . , α b+2t−1 } is selected. Here, it is possible to select any integer as the value of b. Consequently, there is a significant number of RS codes that are different from each other and that have the same t-byte correction.

From the viewpoint of system development, such a level of freedom is preferred. From the viewpoint of standardization, this level is not sufficient. From the demand on the correction power, etc., usually, a Galois field GF(2 8 ) having 2 8 elements is usually adopted, while the other parameters may take different values. It is natural that the code length and correction power depend on the specifications demanded. Among the cited differences, that having the most significant influence is the difference of the field generation polynomial. For example, when RS coding/decoding devices corresponding to two schemes are formed, because their field generation polynomials are different from each other, their multipliers of the Galois field are also different from each other. Consequently, there is no way to share them. In particular, in order to meet a higher correction power, the proportion of the aforementioned multiplier of the Galois field in the circuit scale is large. In the conventional method, the multipliers of the Galois field corresponding to the two schemes have to be respectively equipped, so that the price of the device is boosted, which is a disadvantage.

As a matter of fact, even in the same field of digital transmission, the field generation polynomial adopted for satellite communications and the field generation polynomial adopted for satellite broadcasts are different. This is mainly due to the difficulty in standardization due to the difference in management between field of communications and the broadcast field. Also, at the time of standardization, there was a low necessity to share the field generation polynomial.

In recent years, studies have made it more and more clear that it is necessary to unify communications and broadcasts. However, once the standardization is completed, it becomes very difficult to change it. Also, the RS code adopted for the recording media is usually developed by the producers, yet in few cases, the same field generation polynomial is adopted by different recording media developed by different producers.

FIG. 11 is a schematic diagram illustrating the conventional RS coding/decoding device that can handle two or more RS codes, that is, RS a code, RS b code, RS x code. It is equipped with multipliers 10 a - 10 x of Galois fields GF a (2 m ) , GF b (2 m ), . . . GF x (2 m ) corresponding to the various field generation polynomials, respectively, as well as multiplication coefficient memory units 11 a - 11 x that store sets of Galois field multiplication coefficient {α a[I] }, {β b[J] }, . . . , χ x{[K] } respectively. The conventional RS coding/decoding device also has inverse element operation circuits 12 a - 12 x for division operations corresponding to the various codes.

In the following description, in order to simplify the description, conventional RS coding/decoding device 1 for handling two RS codes, that is, the RS a code and RS b code, will be described. In this case, for both the RS a code and RS b code, the correction power is taken as a t-byte correction.

FIG. 12 is a diagram illustrating the polynomial remainder operation circuit 202 that forms conventional RS coding/decoding device 1 . In remainder operation circuit 202 , the set of Galois field multiplication coefficient {α ae[i] }, i=0−L is contained in the aforementioned Galois field's multiplication coefficient set {α a[I] }, and the Galois field's multiplication coefficient set {β be[j] }, j=0−L is contained in the aforementioned set of Galois field multiplication coefficient {β b[J] }. L is 2t−1 or 2t (same in the following).

As shown in FIG. 12 , the polynomial operation circuit 202 has multipliers 203 - 0 to 203 -L, multipliers 208 - 0 to 208 -L, switches 204 - 0 to 204 -L, registers 205 - 0 to 205 -L, adders 206 - 0 to 206 -L, and adder 207 .

Switches 204 - 0 - 204 -L select multipliers 203 - 0 to 203 -L in the case of RS a coding, and they select multipliers 208 - 0 to 208 -L in the case of RS b coding.

The RS decoding device usually comprises a syndrome operation circuit, error-position polynomial and evaluating polynomial operation circuit, error-position detector, evaluation value detector, and correction execution circuit. Among these, for the aforementioned error-position polynomial operation circuit and evaluating polynomial operation circuit, the Euclid and the Berlekamp-Massey algorithm are known algorithms.

FIG. 13 is a conventional structural example of syndrome operation circuit 209 that can handle the aforementioned two RS codes. In this case, the set of Galois field multiplication coefficient {α as[I] }, I=0˜L is contained in said {α a[I] }, and the Galois field's multiplication coefficient assembly {β bs[j] }, j=0˜L is contained in said {β b[J] }.

As shown in FIG. 13 , syndrome operation circuit 209 has multipliers 213 - 0 to 213 -L, switches 214 - 0 to 214 -L, registers 215 - 0 to 214 -L, adders 216 - 0 to 216 -L, and multipliers 217 - 0 to 217 -L.

Switches 214 - 0 to 214 -L select multipliers 213 - 0 to 213 -L in the case of RS a coding, and they select multipliers 217 - 0 to 217 -L in the case of RS b coding.

FIG. 14 is a diagram illustrating a conventional structural example of polynomial divider 221 , one of the principal structural elements of the operation circuit of the error-position polynomial and evaluation polynomial that can handle the aforementioned two RS codes.

As shown in FIG. 14 , polynomial divider 221 has switches 222 - 0 to 222 -L, multipliers 223 - 0 to 223 -L, multipliers 228 - 0 to 228 -L, registers 225 - 0 to 225 -L, registers 224 - 0 to 224 -L, adders 226 - 0 - 226 -L, registers 227 , 229 , inverse element operation circuits 231 , 232 , multipliers 230 , 231 , and switch 234 .

Switches 222 - 0 to 222 -L select multipliers 223 - 0 to 223 -L in the case of RS a coding, and they select multipliers 228 - 0 to 228 -L in the case of RS b coding. Also, switch 234 selects multiplier 230 in the case of RS a coding, and selects multiplier 231 in the case of RS b coding.

FIG. 15 is a diagram illustrating a conventional structural example of polynomial multiplier 241 , one of the principal structural elements of the operation circuit of the error-position polynomial and evaluation polynomial that can handle the aforementioned two RS codes.

As shown in FIG. 15 , polynomial multiplier 241 has multipliers 243 - 0 to 243 -L, multipliers 248 - 0 to 248 -L, switches 242 - 0 to 242 -L, registers 245 - 0 to 245 -L, adders 246 - 0 to 246 -L, and registers 247 - 0 to 247 -L.

Switches 242 - 0 to 242 -L select multipliers 243 - 0 to 243 -L in the case of RS a coding, and they select multipliers 248 - 0 to 248 -L in the case of RS b coding.

FIG. 16 is a diagram illustrating a structural example of conventional error-position detecting circuit 251 that can handle the aforementioned two RS codes.

As shown in FIG. 16 , error-position detecting circuit 251 has multiplier 252 - 0 to 252 -n, multipliers 258 - 0 to 258 -n, switches 252 - 0 to 252 -n, registers 255 - 0 to 255 -n, adders 256 - 1 to 256 - 0 , hand detecting circuit 257 .

Switches 252 - 0 to 252 -n select multipliers 252 - 0 to 252 -n in the case of RS a coding, and they select multipliers 258 - 0 to 258 -n in the case of RS b coding.

In this case, a set of Galois field multiplication coefficient {α ac[I] }, I=0˜n=t is contained in said {α a[I] }, and a set of Galois field multiplication coefficient {β bc[j] }, j=0˜n=t is contained in said {β b[J] }. When the erasure correction is carried out, one has I=0˜n=2t, j=0˜n=2t.

FIG. 17 is a diagram illustrating a conventional structural example of evaluation value detecting circuit 261 that can handle said two RS codes.

As shown in FIG. 17 , evaluation value detecting circuit 261 has multipliers 262 - 0 to 262 -(n−1), multipliers 267 - 0 to 267 -(n−1), switches 262 - 0 to 262 -(n−1), registers 265 - 0 to 265 -(n−1), and adders 266 - 1 to 266 -(n−1).

Switches 262 - 0 to 262 -(n−1) select multipliers 262 - 0 to 262 -(n−1) in the case of RS, coding, and they select multipliers 267 - 0 to 267 -(n−1) in the case of RS b coding.

In this case, a set of Galois field multiplication coefficient {α av[I] }, I=0˜n−1 is contained in said {α a[I] }, and a set of Galois field multiplication coefficient {β bv[j] }, j=0˜n−1 is contained in said {β b[J] }.

In this way, the conventional RS coding/decoding device that can handle two or more RS codes is formed by necessarily having the Galois field multipliers and inverse element operation circuits corresponding to the respective field generation polynomials and for use in switching.

The purpose of this invention is to solve the aforementioned problems of the prior art by providing a type of Reed-Solomon coding method and a device with a reduced size and lower cost.

Another purpose of this invention is to provide a Reed-Solomon decoding method and device with a reduced size and lower cost.

SUMMARY OF THE INVENTION

In order to solve the aforementioned problems of the prior art, the Reed-Solomon coding device of this invention is one that can handle multiple RS (Reed-Solomon) codes using different field generation polynomials, and it has the following means: a Galois field transformation means that transforms the input data into the data of the prescribed Galois field; a coding means that performs coding processing of the aforementioned transformed data by means of the aforementioned Galois field after transformation; and a Galois field inverse transformation means that undertakes inverse transformation of the aforementioned Galois field of coded data to the Galois field before transformation.

In the Reed-Solomon coding device of this invention, by setting the Galois field transformation means and Galois field inverse transformation means, it is possible to perform the coding processing by means of the prescribed Galois field in the coding means for any of multiple RS codes. As a result, there is no need to set individual multipliers and inverse element operation units corresponding to all of the multiple RS codes, respectively, and the size of the circuit can be significantly reduced.

Also, in the Reed-Solomon coding device of this invention, the aforementioned coding means preferably has a multiplier corresponding to the aforementioned Galois field after transformation.

Also, in the Reed-Solomon coding device of this invention, preferably the aforementioned multiple RS codes are the RS a code and RS b code using different field generation polynomials; the coding symbols are Galois fields GF a (2 m ) and GF b (2 m ) extended based on m-th order field generation polynomials Gp a (x) and Gp b (X) which are different from each other, on Galois field GF(2), respectively; for α as the root of said Gp a (x) and as the primitive element of said GF a (2 m ), and for β as the root of said Gp b (x) and as the primitive element of said GF b (2 m ), the following equation (25) is established; said RS b code has power of t-symbol correction, and its code generation polynomial G cb (x) is represented by the following equation (26); when the aforementioned input data are coded by said RS b code, said Galois field transformation means transforms the Galois field of the aforementioned input data from said Galois field GF b (2 m ) into said Galois field GF a (2 m ); the aforementioned coding means performs coding corresponding to the following equation (27) as a polynomial that transforms said code forming polynomial G cb (x) into said Galois field GF a (2 m ); the aforementioned Galois field inverse transformation means undertakes inverse transformation of the aforementioned Galois field of coded data from said Galois field GF a (2 m ) into said Galois field GF b (2 m ).

Gp b (α p )=0  Equation 25 $$ Equation ⁢   ⁢ 26   Gc b ⁡ ( x ) = ∏ j = 0 L ⁢ ( x + β q ⁡ ( b + j ) ) , L = 2 ⁢ t - 1 ,   ⁢ or ⁢   ⁢ 2 ⁢ t ( 26 ) $$ Equation ⁢   ⁢ 27   Gc ba ⁡ ( x ) = ∏ j = 0 L ⁢ ( x + α pq ⁡ ( b + j ) ) , L = 2 ⁢ t - 1 ,   ⁢ or ⁢   ⁢ 2 ⁢ t ( 27 )

Also, in the Reed-Solomon coding device of this invention, preferably, with the transposed matrix represented as ( . . . ) T , when m values among the 2 m input/output relationships are as follows: with respect to m-bit input (00 . . . 0001) T , m-bit output A 0 =(00 . . . 001) T is performed; with respect to m-bit input (00 . . . 0010) T , m-bit output A 1 =(A 1,m−1 , A 1,m−2 , . . . A 1,0 ) T is performed; with respect to m-bit (00 . . . 0100) T m-bit output A 2 =(A 2,m−1 , A 2,m−2 , . . . A 2,0 ) T is performed, with respect to m-bit input (01 . . . 0000) T , m-bit output A m−2 =(A m−2,m−1 , A m−2,m−2 , . . . A m−2,0 ) T is performed; and with respect to m-bit input (10 . . . 0000) T , m-bit output A m−1 =(A m−1,m−1 , A m−1,m−2 , . . . A m−1,0 ) T is performed; with m by m matrix [H ba ] being defined by the following equation (28), the aforementioned Galois field transformation means performs operation processing corresponding to the following equation (29) with respect to said m-bit input data D b-in to generate m-bit output data D a-out .

[H ba ]=(A m−1 A m−2 . . . A 2 A 1 A 0 )  Equation 28

D a — out =[H ba ]×D b — in   Equation 29

Also, for the Reed-Solomon coding device of this invention, preferably, the aforementioned Galois field inverse transformation means performs operation processing corresponding to the following equation (30) to generate m-bit output data D b-out when the inverse matrix of said matrix [H ba ] is [H ab ].

D b — out =[H ab ]×D a — in   Equation 30

The Reed-Solomon decoding device of this invention is one that can handle multiple RS codes using different field-forming polynomials, and there are the following means: a Galois field transformation means that transforms the input coded data into the coded data in of the prescribed Galois field; a decoding means that performs decoding processing of the aforementioned transformed coded data by means of the aforementioned Galois field after transformation; and a Galois field inverse transformation means that undertakes inverse transformation of the aforementioned Galois field of decoded data to the Galois field before transformation.

In the Reed-Solomon decoding device of this invention, by setting the Galois field transformation means and Galois field inverse transformation means, it is possible to perform the decoding processing by means of the prescribed Galois field in the decoding means for any of multiple RS codes. As a result, there is no need to set individual multipliers and inverse element operation units corresponding to all of the multiple RS codes, respectively, and the size of the circuit can be significantly reduced.

In the Reed-Solomon decoding device of this invention, the aforementioned Galois field transformation means preferably has a multiplier corresponding to the aforementioned Galois field after transformation.

Also, for the Reed-Solomon decoding device of this invention, preferably, the aforementioned multiple RS codes are the RS a code and RS b code using different field generation polynomials; the coding symbols are Galois fields GF a (2 m ) and GF b (2 m ) extended based on m-th order field generation polynomials Gp a (x) and Gp b (x), which are different from each other, on Galois field GF(2), respectively; for α as the root of said Gp a (x) and as the primitive element of said GF a (2 m ) and for β as the root of said Gp b (x) and as the primitive element of said GF b (2 m ), the following equation (31) is established; said RS b code has power of t-symbol correction, and its code generation polynomial G cb (x) is represented by the following equation (32); when the aforementioned input coded data are decoded, said Galois field transformation means transforms the Galois field of the aforementioned coded data from said Galois field GF b (2 m ) into said Galois field GF a (2m); the aforementioned decoding means performs decoding corresponding to the following equation (33) as a polynomial that transforms said code forming polynomial G cb (x) into said Galois field GF a (2 m ); and the aforementioned Galois field inverse transformation means undertakes transformation of the aforementioned Galois field of decoded data from said Galois field GF a (2 m ) into said Galois field GF b (2 m )

  Gp b (α p )=0  Equation 31 $$ Equation ⁢   ⁢ 32   Gc b ⁡ ( x ) = ∏ j = 0 L ⁢ ( x + β q ⁡ ( b + j ) ) , L = 2 ⁢ t - 1 ,   ⁢ or ⁢   ⁢ 2 ⁢ t ( 32 ) $$ Equation ⁢   ⁢ 33   Gc ba ⁡ ( x ) = ∏ j = 0 L ⁢ ( x + α pq ⁡ ( b + j ) ) , L = 2 ⁢ t - 1 ,   ⁢ or ⁢   ⁢ 2 ⁢ t ( 33 )

Also, for the Reed-Solomon decoding device of this invention, preferably, with the transposed matrix represented as ( . . . ) T , when m values among the 2 m input/output relationships are as follows: with respect to m-bit input (00 . . . 0001) T , m-bit output A 0 =(00 . . . 001) T is performed, with respect to m-bit input (00 . . . 0010) T , m-bit output A 1 =(A 1,m−1 , A 1,m−2 , . . . A 1,0 ) T is performed, with respect to m-bit input (00 . . . 0100) T , m-bit output A 2 =(A 2,m−1 , A 2,m−2 , . . . A 2,0 ) T , is performed, with respect to m-bit input (01 . . . 0000) T , m-bit output A m−2 =(A m−2,m−1 , A m−2,m−2 , . . . A m−2,0 ) T is performed, and with respect to m-bit input (10 . . . 00000) T , m-bit output A m−1 =(A m−1,m−1 , A m−1,m−2 , . . . A m−1,0 ) T is performed, with m by m matrix [H ba ] being defined by the following equation (34), the aforementioned Galois field transformation means performs operation processing corresponding to the following equation (35) with respect to said m-bit input data D b-in to generate m-bit output data D a-out .

[ H ba ]=( A m−1 A m−2 . . . A 2 A 1 A 0 )  Equation 34

  D a — out =[H ba ]×D b — in   Equation 35

Also, for the Reed-Solomon coding device of this invention, preferably, the aforementioned Galois field inverse transformation means performs operation processing corresponding to the following equation (36) to generate m-bit output data D b-out when the inverse matrix of said matrix [H ba ] is [H ab ].

D b — out =[H ab ]×D a — in   Equation 36

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the RS coding/decoding device in an embodiment of this invention.

FIG. 2 is a diagram illustrating the transformation table in the input-side transformation circuit and output-side transformation circuit shown in FIG. 1 .

FIG. 3 is a diagram illustrating the constitution of the operation circuit used in the RS coding core unit shown in FIG. 1 .

FIG. 4 is a diagram illustrating the constitution of the syndrome operation circuit used in the RS decoding unit shown in FIG. 1 .

FIG. 5 is a diagram illustrating the constitution of the divider used in the RS decoding unit shown in FIG. 1 .

FIG. 6 is a diagram illustrating the constitution of the multiplier used in the RS decoding unit shown in FIG. 1 .

FIG. 7 is a diagram illustrating the constitution of the position-detecting circuit used in the RS decoding core unit shown in FIG. 1 .

FIG. 8 is a diagram illustrating the constitution of the evaluation value detecting circuit used in the RS decoding core unit shown in FIG. 1 .

FIG. 9 is a diagram illustrating the constitution of another example of the RS coding/decoding device in an embodiment of this invention.

FIG. 10 is a diagram illustrating the constitution of another example of the RS coding/decoding device in an embodiment of this invention.

FIG. 11 is a schematic diagram illustrating the conventional RS coding/decoding device.

FIG. 12 is a diagram illustrating the constitution of the modulo operation circuit used in the conventional RS coding core unit shown in FIG. 11 .

FIG. 13 is a diagram illustrating the constitution of the syndrome circuit used in the conventional RS decoding core unit shown in FIG. 11 .

FIG. 14 is a diagram illustrating the constitution of the divider used in the conventional RS decoding core unit shown in FIG. 11 .

FIG. 15 is a diagram illustrating the constitution of the multiplier used in the conventional RS decoding core unit shown in FIG. 11 .

FIG. 16 is a diagram illustrating the constitution of the position-detecting circuit used in the conventional RS decoding core unit shown in FIG. 11 .

FIG. 17 is a diagram illustrating the constitution of the evaluation value detecting circuit used in the conventional RS decoding core unit shown in FIG. 11 .

REFERENCE NUMERALS AND SYMBOLS AS SHOWN IN THE DRAWINGS

101 represents the RS coding/decoding device, 101 the remainder operation circuit, 109 the syndrome operation circuit, 111 a to 111 x the multiplication coefficient memory unit, 112 the RS coding/decoding core units, 113 - 0 to 113 -L the multipliers, 114 , 118 , 121 the switches, 115 the inverse element operation circuit, 119 a - 119 x the output-side transformation circuits, 121 the polynomial divider, 141 the polynomial multiplier, 151 the error-position-detecting circuit, 161 the evaluation-value-detecting circuit.

Description of the Embodiments

FIG. 1 is a schematic diagram illustrating RS coding/decoding device 101 in this embodiment.

RS coding/decoding device 101 can handle two or more RS codes, that is, RS a code, RS b code, . . . RS x code.

As shown in FIG. 1 , there are the following parts: Galois field multiplier 113 corresponding to GF a (2 m ); multiplication coefficient memory units 111 a to 111 x that store the Galois field multiplication coefficient sets {α a[I] }, {α b[J] }), . . . {α x[K] } corresponding to the various code-forming polynomials, respectively; RS coding/decoding core unit 112 ; inverse element operation circuit 115 ; input-side transformation circuits 116 b to 116 x ; output-side transformation circuits 119 b to 19 x ; and switches 114 , 118 , 121 .

As shown in FIG. 1 , RS coding/decoding device 101 has a constitution with input-side transformation circuits 116 b to 116 x and output-side transformation circuits 119 b to 119 x for the transformation of Galois field attached to the input side and output side of RS coding/decoding unit 112 , respectively. Also, in RS coding/decoding unit 112 , the multiplication coefficient corresponding to the use of switch 114 is output from multiplication coefficient memory units 111 a to 111 x. For switch 114 , the switch is used by applying a certain RS code.

In RS coding/decoding device 101 , when coding of the RS a code is performed, the data are sent through channels 117 , 120 without performing transformation processing in input-side transformation circuits 116 b to 116 x and output-side transformation circuits 119 a to 119 x as Galois field transformation circuits. Also, from multiplication coefficient memory unit 111 a , multiplication coefficient {α a[I] } is output to RS coding/decoding unit 112 . In the case of RS decoding, similarly, the same aforementioned input-side transformation circuit and output-side transformation circuit can be used.

In the following, for simplicity, the case of RS coding/decoding device 101 that can handle two RS codes, that is, the RS a code and RS b code, will be presented as an example. In this case, for both codes, the correction power is taken as a t-byte correction. In this case, as shown in FIG. 1 , input-side transformation circuit 116 b and output-side transformation circuit 119 b alone are used as the input-side transformation circuit and output-side transformation circuit, respectively. As the multiplication coefficient memory unit, multiplication coefficient memory units 111 a and 111 b alone are used.

In this embodiment, as an example, RS coding and decoding are performed with q=88 and m=8 in said formulas (25)-(30).

In this embodiment, the main topic is to perform coding/decoding for said RS b code and to form its device. Consequently, for the aforementioned RS a code, the only condition required is to have the order number of the field generation polynomial equal to said RS b code. Also, in order to simplify the explanation of this embodiment, the correction power of said RS a code is taken as a t-byte correction just as said RS b code.

RS a Code

As said RS a code, the field generation polynomial on GF(2) that defines the coding symbol and forms ground field GF a-B (2 8 ) is defined by the following equation (37).

Gp a ( x )= x 8 +x 4 +x 3 +x 2 +1  Equation 37

In addition, the code generation polynomial of said RS a code is defined by the following equation (38). $$ Equation ⁢   ⁢ 38   Gc a ⁡ ( x ) = ∏ j = 0 L ⁢ ( x + α a + i ) , L = 2 ⁢ t - 1 ,   ⁢ or ⁢   ⁢ 2 ⁢ t ( 38 )

In this case, the coefficient of x is the element of said GF a-B (2 8 ), and extension field GF a-E (2 8 ) of the code is equal to ground field GF a-B (2 8 ). That is, in this embodiment, said Galois field GF a (2 8 ) as the object of transformation corresponds to Gf a-B (2 8 )=Gf a-E (2 8 ).

Also, α is taken as the root of said Gp a (x) and as the primitive element over said GF a (2 8 )=GF a-B (2 8 ). To simplify the explanation, α is represented by a column vector (00000010) T . Also, from said equation (37), the following equation (39) is established.

α 8 =α 4 +α 3 +α 2 1  Equation 39

Its column vector representation is (α 8 ) a =(00011101) T . Here, (X) a represents the column vector representation of said GF a (2 8 ). Also, one has (α 0 ) a =(1) a =(00000001) T .

RS b Code

As said RS b code, the field generation polynomial on GF(2) that defines the coding symbol and forms the ground field is defined by the following equation (40).

  Gp b ( x )= x 8 +x 5 +x 3 +x 2 1  Equation 40

In addition, said RS b -code generation polynomial is defined by the following equation (41). $$ Equation ⁢   ⁢ 41   Gc b ⁡ ( x ) = ∏ j = 0 L ⁢ ( x + β 88 ⁢ ( b + j ) ) , L = 2 ⁢ t - 1 ,   ⁢ or ⁢   ⁢ 2 ⁢ t ( 41 )

Equation (41) corresponds to the case in which q=88 in said equation (26). Strictly speaking, this RS code is contained in the Goppa code. Consequently, although the coefficient of x of said equation (41) can be represented by the element of said GF b-B (2 8 ), it is different from GF b-B (2 8 ) as the ground field of extension field GF b-B (2 8 ) of the code. In this embodiment, said Galois field GF b (2 8 ) as the object of transformation corresponds to GF b-B (2 8 ). The Euclidean decoding method of the aforementioned Goppa code is described in the reference “Sugiyama, Kasahara, Hirasawa, A method for solving key equation for decoding Goppa codes, Inf. and C ont., 27, 1975,” and its erasure correction method is described in detail in the reference “Sugiyama, Kasahara, Hirasawa, Namekawa: An erasures-and-errors decoding algorithm for Goppa codes, IEEE Trans. Infrom. Theory, 1976.”

Also, β is taken as the root of said Gp b (x) and as the primitive element over said GF b (2 8 )=GF b-B (2 8 ). For simplifying the explanation, β is also represented by the same column vector (00000010) T . Also, from said equation (40), the relationship represented by the following equation (42) is established. $$ Equation ⁢   ⁢ 42   β 8 = β 5 + β 3 + β 2 + 1 β 9 = β × β 8 = β 6 + β 4 + β 3 + β β 10 = β × β 9 = β 7 + β 5 + β 4 + β 2 β 11 = β × β 10 = β 8 + β 6 + β 5 + β 3 = β 5 + β 3 + β 2 + 1 + β 6 + β 5 + β 3 = β 6 + β 2 + 1 ( 42 )

Its column vector representation is (β 8 ) b =(00101101) T . Here, (X) b represents the column vector representation of said GF b (2 8 ). Also, one has (β 0 ) b =(1) b =(00000001) T .

For the coding over said RS b code, it can be realized by performing transformation of the code generation polynomial at the same time as the transformation of the Galois field; the transformation itself is relatively simple.

In the following, an explanation will be made on the various structural elements of RS coding/decoding device 101 and the circuit that forms RS coding/decoding unit 112 shown in FIG. 1 .

Input-side Transformation Circuit and Output-side Transformation Circuit

For example, the relationship between α and β may be derived as follows. However, Gp a (x) is an original polynomial on GF(2), and it has 8 roots of α, α 2 , α 4 , α 8 , α 16 , α 32 , α 64 , α 128 . Similarly, the original polynomial Gp a-p (x) with α P as a root has a total of 8 roots, including α P as well as the following roots: α 2P , α 4P , α 8P , α 16P , α 32P , α 64 , α 128P , and the following equation (43) is established.

  Gp a — p ( x )=( x=α p )( x+α 4p )( x+α 8p ) . . . ( x+α 64p )( x+α 128p )  Equation 43

Supposing that p=241 in said equation (43), the following equation (44) is established.

Gp a — p ( x )=α 0 X 8 +α 0 x 5 +α 0 x 3 +α 0 x 2 +α 0   Equation 44

With α 0 =1 over GF(2), the right-hand side of equation (44) is in agreement with the right-hand side of said equation (40). That is, said Gp a-p (x) and said Gp b (x) have the same roots on GF(2).

Also, when calculation is performed over said GF a (2 8 ), the following equation (45) is established.

Gp b (α 241 )=0  Equation 45

In this way, α 241 of said Galois field GF a (2 8 ) corresponds to β of said Galois field GF b (2 8 ). More specifically, from said equation (45), the following equation (46) is established.

 (α 241 ) 8 =(α 241 ) 5 +(α 241 ) 3 +(α 241 ) 2 +1

(α 241 ) 9 =α 241 ×(α 241 ) 8 =(α 241 ) 6 +(α 241 ) 4 +(α 241 ) 3 +α 241

(α 241 ) 10 =α 241 ×(α 241 ) 9 =(α 241 ) 7 +(α 241 ) 5 +(α 241 ) 4 +(α 241 ) 2

(α 241 ) 11 =α 241 ×(α 241 ) 10 =(α 241 ) 6 +(α 241 ) 2 +1  Equation 46

Based on said equation (46), any element α 241 of said Galois field GFa(2 8 ), with z representing any integer, can be represented by a linear combination of (α 241 ) 7 , (α 241 ) 6 , . . . , (α 241 ) 2 , α 241 and 1.

That is, in the case of the following equation (47), the relationship of the following equation (48) is established. $$ Equation ⁢   ⁢ 47   β z = ∑ i = 0 7 ⁢ B z , i ⁢ β i ( 47 ) $$ Equation ⁢   ⁢ 48   α 241 ⁢ z = ∑ i - 0 7 ⁢ B z , i ⁢ α 241 ⁢ i ( 48 )

In said formulas (47) and (48), B z,i =0 or 1.

In this way, over said GF a (2 8 ), α 241z behaves just as βz over Galois field GF b (2 8 ). From a contrary point of view, βz over said Galois field GF b (2 8 ) corresponds to α 241z over said Galois field GF a (2 8 ) .

In input-side transformation circuit 116 b , which is transformed from said Galois field GF b (2 8 )=GF b-B (2 8 ) into said Galois field GF a (2 8 )=GB a-B (2 8 ), any element βz over GF b (2 8 ) is transformed into element α 241z over GF a (2 8 ), and 0 is transformed to 0 remains 0. According to the rules of operation over said GF a (2 8 ), the transformed series defined over said GF a (2 8 ) can be used as a multiplier in the RS coding/decoding processing to be explained later. More specifically, this transformation operation is performed for each vector representation. The transformation table of input-side transformation circuit 116 b is shown in FIG. 2 . Also, in output-side transformation circuit 119 b as well, the transformation table shown in FIG. 2 is used.

According to the transformation table shown in FIG. 2 , for input-side transformation circuit 116 b shown in FIG. 1 , there is a ROM that outputs the 8-bit data corresponding to 0, 1, α 241 , α 241x2 , α 241x3 . . . according to the 8-bit address input corresponding to 0, 1, β 1 , β 2 , β 3 . . . .

Also, the series, as a result of processing over said Galois field GF a (2 8 ), is transformed into the series of the original Galois field GF b (2 8 ) by means of output-side transformation circuit 119 b , which transforms any element α 241z over GF a (2 8 ) to the series of GF b (2 8 ) and transforms 0 to 0. Output-side transformation circuit ( 119 b ), which is transformed from said Galois field GF a (2 8 ) into said Galois field GF b (2 8 ), also has a ROM, which outputs 8-bit data corresponding to 0, 1, β 1 , β 2 , β 3 . . . with respect to the 8-bit address input corresponding to 0, 1, α 241 , α 241×2 , α 241×3 . . . by using the transformation table shown in FIG. 2 .

Also, with the following equation (49) being established over said Galois field GF b (2 8 ), it is possible to obtain the transformation table shown in FIG. 2 with the aforementioned main points.

  GP a (β 91 )=0  Equation 49

Said equations (45) and (49) form a pair in the sense that the same transformation table is obtained. In addition, there is also the pair of Gp b (α 31 )=0 and Gp a (β 181 ), the pair of Gp b (α 62 ) and Gp a (β 218 ), etc. There is a total of 8 groups of pairs. The RS coding/decoding device of this embodiment may adopt the transformation table using any of these pairs.

The aforementioned Galois field transformation may be described even simpler using 8×8 matrices.

Before an explanation of the example, the general rule of the element transformation will be explained.

Theorem 1

The m by m matrix [H ba (z)], which is transformed from Galois field GF b (2 m ) to Galois field GF a (2 m ), is defined by the following equation (50).

(α pz ) a=[H ba ( z )](β z ) b   Equation 50

In said equation (50), z represents any integer and (X) a is the column vector representation of element X over said Galois field GF a (2 m ). Similarly, (Y) b is the column representation of element Y over said Galois field GF b (2 m ). That is, they form mxl matrix; α represents the original element of said Galois field GF a (2 m ), and it is the root of the m-th order field generation polynomial Gp a (x) on GF(2); β represents the original element over said Galois field GF b (2 m ), and it is the root of the m-th order field generation polynomial Gp a (x) over GF(2), with (β) b =(000 . . . 010) T .

Also, the following equation (51) is established over Gp a (2 m ).

Gp b (α p )=0  Equation 51

In this case, the following equation (52) is established.

[H ba ( z )]=[ H ba ]=[(α p(m−1) ) a (α p(m−2 ) a . . . (α 2p ) a (α p ) a (α 0 ) a]   Equation 52

That is, said equation (50) is established independently of the value of z.

This “Theorem 1” can be proved as follows.

First of all, with the following equation (53) being established, matrix [H ba ] of said equation (52) is used, and the following equation (54) is established.

(β 0 ) b =(00 . . . 001) T

(β 1 ) b =(00 . . . 010) T

(β 2 ) b =(00 . . . 100) T

(β m−2 ) b =(01 . . . 000) T

(β m−1 ) b =(10 . . . 000) T   Equation 53

 (α 0 ) a=[H ba ](β 0 ) b

(α p ) a=[H ba ](β 1 ) b

(α 2p ) a=[H ba ](β 2 ) b

(α p(m−2) ) a=[H ba ](β m−2 ) b

(α p(m−1) ) a=[H ba ](β m−1 ) b   Equation 54

Also, for any element β z over said Galois field GF b (2 m ), the following Equation (55) is established. $$ Equation ⁢   ⁢ 55   β z = ∑ i - 0 m1 ⁢ B z , i ⁢ β i ( 55 )

where B z,i =0 or 1, and z represents any integer. As said equation (51) is established, the following equation (56) can be obtained. $$ Equation ⁢   ⁢ 56   α pz = ∑ i = 0 m - 1 ⁢ B z , i ⁢ α pi ( 56 )

It can also be derived from said equations (47) and (48) Consequently, for this representation with vectors on both sides, said equation (54) can be broken down to the following equation (57). $$ Equation ⁢   ⁢ 57   ( α pz ) ⁢ a = ∑ i - 0 m - 1 ⁢ B z , i ⁡ ( α pi ) ⁢ a = ∑ i = 0 m1 ⁢ B z , i ⁡ [ H ba ] ⁢ ( β i ) ⁢ b = [ H ba ] ⁢ ∑ i = 0 m - 1 ⁢ B z , i ⁡ ( β i ) ⁢ b ( 57 )

In addition, when the vector representations on both sides of said equation (55) are substituted into said equation (57), the following equation (58) is obtained.

(α pz ) a=[H ba ](β z ) b   Equation 58

This is the end of the proof of “Theorem 1.”

Also, for [H ba ] by said equation (55), the following equation (59) is established with respect to (0) a =(000 . . . 000) T and (0) b =(000 . . . 000) T .

( 0 ) a=[H ba ]( 0 ) b   Equation 59

That is, all of the elements over said Galois field Gp a (2 m ) are transformed into all of the elements over said Galois field Gp b (2 m ).

The aforementioned can be summarized as follows: when m values among the 2 m input-output relationships in the input-side transformation process include m-bit output A 0 =(00 . . . 001) T with respect to m-bit input (00 . . . 0001) T , m-bit output A 1 (A 1,m−1 , A 1,m−2 , . . . A 1,0 ) T , with respect to m-bit input (00 . . . 0001) T , m-bit output A 2 =(A 2,m−1 , A 2,m−2 , . . . , A 2,0 ) T with respect to m-bit input (01 . . . 0001) T , m-bit output A m−2 =(A m−2,m−1 , A m−2,m−2 , . . . , A m−2,0 ) T with respect to m-bit input (10 . . . 0000) T , and m-bit output A m−1 =(A m−1,m−1 , A m−1,m−2 , . . . , A m−1,0 ) T with respect to m-bit input (10 . . . 0000) T , the m by m matrix is defined as the following equation (60).

[H ba ]=( A m−1 A m−2 . . . A 2 A 1 A 0 )  Equation 60

The aforementioned input-side transformation process is realized in the process of calculation by the following equation (61) for m-bit D a-out with respect to the input m-bit D b-in .

D a — out =[H ba ]×D b — in   Equation 61

Input-side transformation circuit 116 is the device for the input-side transformation process explained in the above.

In the following, when m=1, q=1, and p=241 for said formulas (49)-(57), specific examples will be presented for input-side transformation circuit 116 b.

The following equation (62) is established based on the transformation table in FIG. 2 .

 (α 0 ) a=A 0 =(00000001) T

(α 241 ) a=A 1 =(01011000) T

(α 241×2 ) a=A 2 =(10010000) T

(α 241×3 ) a=A 2 =(11110010) T

(α 241×4 ) a=A 6 =(00001110) T

(α 241×5 ) a=A 2 =(00110111) T

(α 241×6 ) a=A 6 =(10110011) T

(α 241×7 ) a=A 7 =(11010101) T   Equation 62

Consequently, from said equation (60), the following equation (63) is established. $$ Equation ⁢   ⁢ 63   [ H ba ] =         =       ⁢ ( ( A 7 A 6 … A 2 A 1 A 0 ) 1 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 ) ( 63 )

In this case, with the input-output relationship represented by said equation (61) becoming the following equation (65) and with the following equation (64) representing each bit, the following equation (66) is established.

  D b — out =( d b — o7 d b — o6 d b — o5 d b — o4 d b — o3 d b — o2 d b — o1 d b — o0 ) T

D a — in =( d a — i7 d a — i6 d a — i5 d a — i4 d a — i3 d a — i2 d a — i1 d a — i0 ) T   Equation 64 $$ Equation ⁢   ⁢ 65   ( d b – ⁢ o7 d b – ⁢ o6 d b – ⁢ o5 d b – ⁢ o4 d b – ⁢ o3 d b – ⁢ o2 d b – ⁢ o1 d b – ⁢ o0 ) = ( 1 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 ) = ( d a – ⁢ i7 d a – ⁢ i6 d a – ⁢ i5 d a – ⁢ i4 d a – ⁢ i3 d a – ⁢ i2 d a – ⁢ i1 d a – ⁢ i0 ) ( 65 )   d b — o7 =d a — i7 XOR d a — i6 XOR d a — i3 XOR d a — i2

d b — o6 =d a — i7 XOR d a — i3 XOR d a — i1

d b — o5 =d a — i6 XOR d a — i5 XOR d a — i3

d b — o4 =d a — i7 XOR d a — i6 XOR d a — i5 XOR d a — i3 XOR d a — i2 XOR d a — i1

d b — o3 =d a — i4 XOR d a — i1

d b — o2 =d a — i7 XOR d a — i5 XOR d a — i4

d b — o1 =d a — i6 XOR d a — i5 XOR d a — i4 XOR d a — i3

d b — o0 =d a — i7 XOR d a — i6 XOR d a — i5 XOR d a — i0   Equation 66

Here, XOR represents exclusive-OR. Consequently, input-side transformation circuit 116 that performs transformation of said equation (66) can be realized by as many as 21 XOR gates.

In the following, an explanation will be made on output-side transformation circuit 119 .

It is possible to derive matrix [H ab ] corresponding to the output-side transformation operation by means of the inverse operation from the transformation table shown in FIG. 2 . Also, it is possible to derive it directly from [H ba ] that has been derived.

That is, in the output-side transformation process, with respect to input m-bit D a-in corresponding to the element over said Galois field Gp a (2 m ), output m-bit D b-out corresponding to the element over said Galois field Gp b (2 m ) is obtained. In generalized equation (61), when D a-out is substituted by D a-in , and D b-in is substituted by D b-out , the following equation (67) is established.

Consequently,

D a — in =[H ba ]×D b — out   Equation 67

When inverse matrix [H ba ] −1 of [H ba ] is multiplied from the left side on both sides of said equation (61), the following equation (68) is obtained. $$ Equation ⁢   ⁢ 68   [ H ba ] - 1 × D a – ⁢ in = [ H ba ] - 1 ⁡ [ H ba ] × D a – ⁢ out = D b – ⁢ out ( 68 )

Consequently, supposing one has the following equation (69), one thus obtains the following equation (70).

[H ab ]=[H ba ] −1   Equation 69

  D b — out =[H ab ]×D a — in   Equation 70

As a specific example, from [H ba ] of said equation (63), the following equation (71) is obtained. $$ Equation ⁢   ⁢ 71   [ H ab ] = [ H ba ] - 1 = ( 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 1 ) ( 71 )

Similarly, based on said matrix [H ab ], output-side transformation circuit 119 can be realized.

In this way, when m=8, the aforementioned input circuit and the aforementioned output transformation circuit can be realized directly by tens of XOR gates, respectively, and the number of gates is in the range of tens to about 100 for each of them.

RS Coding/Decoding Core Unit

In the following, a detailed explanation will be presented on each of the circuits that form RS coding/decoding core unit 112 .

Remainder Operation Circuit

In the following, the embodiment of the polynomial's remainder operation circuit as a principal structural element of the RS coding device will be presented. FIG. 1 illustrates the case in which the RS coding/decoding core unit has an RS coding function. The Galois field multiplier that form the polynomial remainder operation circuit originally is present corresponding to the RS a code. When coding of the RS b code is to be performed, because data sequence of D a -out transformed by input-side transformation circuit 116 b corresponds to the element over Galois field Gp a (2 m ), the multiplication operation of the Galois field follows the multiplication rule on Gp a (2 m ). Consequently, it is possible to make use of the same multiplier to perform coding of the RS b code.

However, as aforementioned, because element Liz over Gp b (2 m ) corresponds to β pz on G pa (2 m ), transformation pertaining to the multiplication coefficient of the Galois field over Gp a (2 m ) is needed. That is, for any integers u and v, multiplication over the Galois field shown by the following equation (72) over said G pb (2 m ) corresponds to the following equation (73) over G pa (2 m ).

β u ×β v =β u+v   Equation 72

α pu ×α pv =α p(u+v)   Equation 73

Clearly, the division operation of the Galois field is similar as aforementioned. Also, for addition (=subtraction) of the Galois field, with reference to said equations (55) and (56), in the case of the following equation (74), the following equation (75) is established based over G pa (2 m ). $$ Equation ⁢   ⁢ 74   β u + β v = ∑ i = 0 m - 1 ⁢ Bu , i , β i + ∑ i = 0 m - 1 ⁢ Bv , i , β i = ∑ i = 0 m - 1 ⁢ ( Bu , i + Bv , i ) ⁢ β i = ∑ i = 0 m - 1 ⁢ Bw , i ⁢   ⁢ β i = β w ( 74 ) $$ Equation ⁢   ⁢ 75   α pu + α pv = ∑ i = 0 m - 1 ⁢ Bu , i , α pi + ∑ i = 0 m - 1 ⁢ Bv , i , α pi = ∑ i = 0 m - 1 ⁢ ( Bu , i + Bv , i ) ⁢ α pi = ∑ i = 0 m - 1 ⁢ Bw , i ⁢   ⁢ α pi = α pw ( 75 )

In this way, usually, for equation F(x)=0 including any arithmetic operation of the Galois field, F(β)=0 over GF b (2 m ) corresponds to F(α p )=0 over GF a (2 m ).

In the process of RS coding, the polynomial remainder operation process is contained by means of the code generation polynomial. For the multiplication coefficient in the polynomial remainder operation circuit of the coding device of the conventional RS b code shown in FIG. 12 , the relationship represented by equation (76) is established. $$ Equation ⁢   ⁢ 76   { β be ⁡ [ j ] } =   ⁢ { β be ⁡ [ 0 ] , β be ⁡ [ 1 ] , β be ⁡ [ 2 ] , ⋯ ⁢   ⁢ β be ⁡ [ L - 1 ] , β be ⁡ [ L ] } =   ⁢ β e ⁡ [ 0 ] , β e ⁡ [ 1 ] , β e ⁡ [ 2 ] , … ⁢   ⁢ β e ⁡ [ L - 1 ] , β e ⁡ [ L ] } ( 76 )

That is, equation (77) is established. $$ Equation ⁢   ⁢ 77   Gcb ⁡ ( x ) =   ⁢ ∏ j = 0 L ⁢ ( x + β q ⁡ ( b + j ) ) =   ⁢ β e ⁡ [ L ] ⁢ x L + β e ⁡ [ L - 1 ] ⁢ x L - 1 + … ⁢   ⁢ β e ⁡ [ 2 ] ⁢ x 2 +   ⁢ β e ⁡ [ 1 ] ⁢ x 1 + β e ⁡ [ 0 ] ⁢ x 0 ( 77 )

Here, L=2t−1 or 2t. From the relationship between said equation and equations (72) to (75), the set {α be[j] } of the corresponding Galois field over GF a (2 m ) should be as in the following equation (78). $$ Equation ⁢   ⁢ 78   { α ⁢   be ⁡ [ j ] } =   ⁢ { α be ⁡ [ 0 ] , α be ⁡ [ 1 ] , α be ⁡ [ 2 ] , ⋯ ⁢   ⁢ α be ⁡ [ L - 1 ] , α be ⁡ [ L ] } =   ⁢ α p × e ⁡ [ 0 ] , α p × e ⁡ [ 1 ] , α p × e ⁡ [ 2 ] , … ⁢   ⁢ α p × e ⁡ [ L - 1 ] , α p × e ⁡ [ L ] } ( 78 )

In this case, corresponding code generation polynomial G cba (x) becomes the following equation (79). $$ Equation ⁢   ⁢ 79   Gc ba ⁡ ( x ) =   ⁢ α p × e ⁡ [ L ] ⁢ x L + α p × e ⁡ [ L - 1 ] ⁢ x L ⁢   ⁢ 1 + … ⁢   ⁢ α p × e ⁡ [ 2 ] ⁢ x 2 +   ⁢ α p × e ⁡ [ 1 ] ⁢ x 1 + α p × e ⁡ [ 0 ] ⁢ x 0 =   ⁢ ∏ j = 0 L ⁢ ( x + α pq ⁡ ( b + j ) ) ( 79 )

That is, the polynomial remainder operation circuit in the RS coding device that can handle the two RS codes in this embodiment becomes that shown in FIG. 3 .

As shown in FIG. 3 , remainder operation circuit 102 has multipliers 103 - 0 to 103 -L, switches 104 - 0 to 104 -L, registers 105 - 0 to 105 -L, and adders 106 - 0 to 106 -L.

For multipliers 103 - 0 to 103 -L, corresponding multiplication coefficients {α be[j] } and multiplication coefficients {α ae[j] } are selectively input by switches 104 - 0 to 104 -L. The multiplication results of the selected multiplication coefficients and input data are output to registers 105 - 0 to 105 -L. More specifically, when RS a coding is performed, by means of switches 104 - 0 to 104 -L, multiplication coefficients {α ae[j] } are output to multipliers 103 - 0 to 103 -L, then multiplication of multiplication coefficient {α ae[j] } and input data is carried out. On the other hand, when RS b coding is performed, by means of switches 104 - 0 to 104 -L, multiplication coefficients {α be[j] } are output to multipliers 103 - 0 to 103 -L, then multiplication of multiplication coefficient {α be[j] } and input data is performed.

Here, multiplication coefficient {α be[j] } is a set of the multiplication coefficient of the Galois field of the remainder operation of the polynomial corresponding to code generation polynomial G cba shown in said equation (79). Also, multiplication coefficient {α ae[j] } is a set of the multiplication coefficient of the Galois field of the remainder operation of the polynomial corresponding to code generation polynomial G cba shown in said equation (38). In FIG. 3 , multipliers 103 - 0 to 103 -L of the Galois field are multipliers over GF a (2 m ), and adders 106 - 0 to 106 -L of the Galois field are adders over GF a (2 m ).

Consequently, in the originally present polynomial remainder operation circuit corresponding to the RS a code, it is possible to realize the polynomial remainder operation circuit corresponding to the RS a code and that corresponding to the RS b code at the same time by simply switching the multiplication coefficient of the Galois field. Also, this embodiment can be adopted for coding of the different RS codes of three or more field generation polynomials as shown in FIG. 1 . Also, it is considered that 0 is contained in the aforementioned set {β be[j] }. However, since 0 p =0, the element of said assembly {α be[j] } corresponding to it is also 0, and the corresponding code generation polynomial G cba (x) is still represented by said equation (79). Also, strictly speaking, this code generation polynomial is contained in the Goppa code.

For the example with m=8, q=88, and p=241, more specifically, assuming that b=120 and L=15 in said equation (78), the following equations (80) and (81) are obtained. $$ Equation ⁢   ⁢ 80   Gc b ⁡ ( x ) = ∏ j = 0 15 ⁢ ( x + β 88 ⁢ ( 120 + j ) ) = β 0 ⁢ x 15 + β 30 ⁢ x 14 + … ⁢   + β 230 ⁢ x 2 + β 30 ⁢ x 1 + β 0 ⁢ x 0 ( 80 )  {β be[j] }={β 0 , β 30 , β 230 , . . . β 30 , β 0 }  Equation 81

On the other hand, the following equation (82) and equation (83) are established. $$ Equation ⁢   ⁢ 82   Gc ba ⁡ ( x ) = ∏ j = 0 15 ⁢ ( x + α 241 × 88 ⁢ ( 120 + j ) ) = α 0 ⁢ x 15 + α 90 ⁢ x 14 + … + α 95 ⁢ x 2 + α 90 ⁢ x 1 + α 0 ⁢ x 0 ( 82 )  {α be[j] }={α 0 =α 241×0 , α 90 =α 241×30 , α 95 =α 241×230 , . . . α 90 =α 241×30 }  Equation 83

In this way, said equations (76)-(79) are embodied.

In this embodiment, it is possible to cause the Galois field multiplier with a relatively large circuit scale to be shared for the coding of both the RS a code and RS b code. More specifically, in the conventional technology, for coding of the RS b code, if L=2t−1, additional 2t Galois field multipliers are needed. In this embodiment of this invention, these new multipliers are not needed. Instead, it is only necessary to switch the multiplication coefficients of the Galois field for performing a division operation of the polynomial. When m=8, the multiplier of the Galois field can be realized by 300-400 gates. Consequently, in this application example, when t=8, it is possible to reduce the number of gates in thousands.

Also, as far as the Galois field addition rule is concerned, for both Galois fields, because their field generation polynomials over the same GF(2) become the grounds of their respective Galois fields, respectively, the same addition rule can be adopted.

RS Decoding

In the following, an explanation will be presented on the embodiment in which the aforementioned RS coding/decoding core unit has an RS decoding function. In the case of RS decoding device, the Galois field transformation circuit in input/output is used in the same way. Because RS decoding has a constitution that is the sum of multiplications of the Galois fields, as well as a multiplication or divider of polynomials, it is possible to realize the shared Galois field multipliers for the RS decoding device that can handle two or more RS codes. That is, it has the set {α a[I] } of Galois field multiplication coefficients corresponding to the decoding of the RS a code and set {α b[J] } of Galois field multiplication coefficients corresponding to the decoding of the RS b code; the sets {α a[I] } and {α b[J] } of the Galois field multiplication coefficients are switched for use depending on whether decoding of the RS a code or of the RS b code is to be performed. Decoding of the RS b code is performed based on said equation (79) over GF a (2 m ). That is, although strictly speaking the decoding of the Goppa code is carried out, as far as the scheme is concerned, for example, the Euclidean decoding method can be used.

Syndrome Operation Circuit

FIG. 4 is a diagram illustrating the embodiment of syndrome operation circuit 109 that can handle said two RS codes. In this case, set {α as[i] }, I=0˜L of Galois field multiplication coefficients is contained in said {α a[I ]}. Also, set {α bs[j] }, j=0˜L of Galois field multiplication coefficients is contained in said {α b[J] }. In addition, for RS b code, as an example, for m=8, q=88, p=241, b=120, L=15, the following equation (84) is presented. $$ Equation ⁢   ⁢ 84   { α bs ⁡ [ j ] } =   ⁢ { α bs ⁡ [ 0 ] , α bs ⁡ [ 1 ] , α bs ⁡ [ 2 ] , … ⁢   ⁢ α bs ⁡ [ L - 1 ] , α bs ⁡ [ L ] } =   ⁢ { α 241 × 88 × 120 , α 241 × 88 × 121 , α 241 × 88 × 122 , …   ⁢ α 241 × 88 × 134 , α 241 × 88 × 135 } =   ⁢ { α 60 , α 103 , α 146 , … ⁢   ⁢ α 152 , α 195 } ( 84 )

As shown in FIG. 4 , syndrome operation circuit 109 has multipliers 113 - 0 to 113 -L, switches 114 - 0 to 114 -L, registers 115 - 0 to 115 -L, and adders 116 - 0 to 116 -L.

For multipliers 113 - 0 to 113 -L, the corresponding multiplication coefficients {α bs[j] } and multiplication coefficient {α as[j] } are selected for input by means of switches 114 - 0 to 114 -L. The results of multiplication of the selected multiplication coefficient and the data from registers 115 - 0 to 115 -L are output to adders 116 - 0 to 116 -L. More specifically, when RS a coding is performed, by means of switches 114 - 0 to 114 -L, various multiplication coefficients {α as[j] } are output to multipliers 113 - 0 to 113 -L, and multiplication is performed for multiplication coefficient {α as[j] } and the data from registers 115 - 0 to 115 -L. On the other hand, when RS b coding is performed, by means of switches 114 - 0 to 114 -L, multiplication coefficients {α bs[j] } are output to multipliers 113 - 0 to 113 -L, and multiplication is performed for multiplication coefficient {α bs[j] } registers 115 - 0 to 115 -L.

Here, multiplication coefficient {α as[j] } is a set of the Galois field multiplication coefficients of the syndrome operation corresponding RS a . Also, multiplication coefficient {α be[j] } is a set of Galois field multiplication coefficients of the syndrome operation corresponding to RS b . In FIG. 4 , Galois field multipliers 113 - 0 to 113 -L are multipliers over GF a (2 m ), and Galois field's adders 116 - 0 to 116 -L are adders over GF a (2 m ).

Divider of Polynomial

FIG. 5 is a diagram illustrating the embodiment of polynomial divider 121 as a principal structural element of the error-position polynomial and evaluation polynomial operation circuit corresponding to the aforementioned two RS codes.

As shown in FIG. 5 , polynomial divider 121 has multipliers 123 - 0 to 123 -L, registers 124 - 0 to 124 -L, registers 125 - 0 to 125 -L, registers 127 , 129 , adders 126 - 0 to 126 -L, multiplier/adder 130 , and inverse operation circuit 131 .

Here, as can be seen from a comparison with the conventional polynomial divider shown in FIG. 14 , there is no need of switching for the Galois field multipliers. Also, there may be only one inverse element operation circuit. That is, when the correction power is the same for the aforementioned two RS codes, they can be entirely realized in the same circuit.

Polynomial Multiplier

FIG. 6 is a diagram illustrating the embodiment of polynomial multiplier 141 as a principal structural element of the error-position polynomial and evaluation polynomial operation circuit corresponding to the aforementioned two RS codes.

As shown in FIG. 6 , polynomial multiplier ( 141 ) has multipliers 143 - 0 to 143 -L, registers 145 - 0 to 145 -L, adders 146 - 0 to 146 -L, and registers 147 - 0 to 147 -L.

Using polynomial multiplier 141 , multiplication is performed according to the multiplication rule over GP a (2 m ). Consequently, when the correction power is the same for the aforementioned two RS codes, the number of the Galois field multipliers can be halved as compared with the conventional polynomial multipliers.

Error-position Detecting Circuit

In the conventional algorithm of the Chien Search, detection of the error-position is performed as follows: values of β −qk corresponding to positions k are substituted in order into error-position polynomial σ b (x) represented by the following equation (85) derived using the aforementioned error-position polynomial operation circuit, as shown by the following equation (86), if the value becomes 0, it is judged that an error is present at said position k. When erasure correction is performed, n= 2 t; when erasure correction is not performed, n=t.

σ b ( x )=σ b[n] x n +σ b[n−1] x n−1 + . . . +σ b[2] x 2 +σ b[1] x 1 +σ b[0] x 0   Equation 85

σ b (β −qk )=0  Equation 86

In this embodiment, β -qk corresponding to said error-position k is equivalent to α p(−qk) over Galois field Gp a (2 m ). For the arithmetic operations, there are the relationships of said equations (72)-(75). Consequently, in this embodiment, the error-position polynomial is represented by the following equation (87).

σ( x )=σ n x n +σ n−1 x n−1 + . . . +σ 2 x 2 +σ 1 x 1 +σ 0 x 0   Equation 87

Here, when the coefficient over Galois field GF b (2 m ) of said equation (86) is σ b[j] =β c[j] or 0, the coefficient over Galois field GF a (2 m ) of said equation (86) is σj=α pc[j] or 0. Consequently, for k, for which said equation (85) is established, the following equation (88) is established.

Equation 88

σ(α −pqk )=0  (88)

In this embodiment, error exists at position k, where equation (88) is established. Also, the same conclusion is obtained when decoding of the Goppa code using the code generation polynomial of said equation (79) is considered as performed using the method described in the aforementioned reference.

FIG. 7 is a diagram illustrating the constitution of error-position detecting circuit 151 in this embodiment corresponding to the aforementioned two RS codes. Error-position detecting circuit 151 is for realizing the algorithm of Chien search corresponding to said equation (87). It is possible to handle the aforementioned two RS codes by simply switching the coefficients. In this case, when the erasure correction is not performed, n=t; set {α ac[I] }, I=0˜t of the Galois field multiplication coefficients is contained in said {α a[I] }, and set {α bc[i] }, i=0˜t of the Galois field multiplication coefficients is contained in said {α b[J] }.

As shown in FIG. 7 , error-position detecting circuit 151 has switches 152 - 0 to 152 - n, multipliers 153 - 0 to 153 - n, registers 155 - 0 to 155 - n, adders 156 - 0 to 156 - n, and 0-detecting circuit 157 . In error-position detecting circuit 151 , based on the detection result of 0-detecting circuit 157 , error-position k is derived.

Here, multipliers 153 - 0 to 153 - n are multipliers of GF a (2 m ), and adders 156 - 1 to 156 - n are adders of GF a (2 m ).

For the RS b code, in the example with m=8, q=88, p=241, b=120, L=15 (t=8), the following equation (89) is established. $$ Equation ⁢   ⁢ 89   { α bc ⁡ [ j ] } =   ⁢ { α bc ⁡ [ 0 ] , α bc ⁡ [ 1 ] , α bc ⁡ [ 2 ] , … ⁢   ⁢ α bc ⁡ [ n - 1 ] , α bc ⁡ [ n ] } =   ⁢ { α 241 × 88 × 255 , α 241 × 88 × 254 , α 241 × 88 × 253 , …   ⁢ α 241 × 88 × 246 , α 241 × 88 × 247 } ( 89 )

As the initial values of the various registers, coefficients σ 0 −σ n of said equation (87) are set, and the values corresponding to the left-hand side of said equation (88) can be calculated successively corresponding to k=0, 1, 2 . . . Also, when erasure correction is performed using the RS b code, j=0˜2t (that is, n=2t).

Evaluation Value Detecting Circuit

In order to make error correction, in addition to error-position k, it is necessary to derive error magnitude e k . The evaluation function is as in the following equation (90).

η( x )=η n−1 x n−1 +η n−2 x n−2 + . . . +η 2 x 2 +η 1 x 1 +η 0 x 0   Equation 90

Supposing that the derivative function of the aforementioned position polynomial is σ′(x), when the decoding of the Goppa code by the code generating polynomial of said equation (79) is carried out according to the aforementioned reference, the magnitude of the aforementioned error is represented by the following equation (91). $$ Equation ⁢   ⁢ 91   e k = α pq ⁡ ( b ⁢   ⁢ 1 ) ⁢ ( - k ) ⁢ η ⁡ ( α - pqk ) σ ′ ⁡ ( α - pqk ) ( 91 )

FIG. 8 illustrates an application example of the proposed evaluation value detecting circuit that can handle the aforementioned two RS codes.

As can be seen from FIG. 8 , evaluation value detecting circuit 161 has switches 162 - 0 to 162 -(n−1), multipliers ( 163 - 0 ) to ( 163 -(n−1)), registers 165 - 0 to 165 -(n−1), and adders 166 - 1 to 166 -(n−1).

Here, when the erasure correction is not carried out, n=t, and set {α av[I] }, i=0˜t of the Galois field multiplication coefficients is contained in said {α a[I] }; set {α bv[j] }, j=0˜t−1 of the Galois field multiplication coefficients is contained in said {α b[J] }.

For multipliers 163 - 0 to 163 -(n−1), by means of switches 162 - 0 to 162 -(n−1), multiplication coefficient {α bv[j] } and multiplication coefficients {α av[j] } are selectively input, then multiplication of the selected multiplication coefficient and the data from registers 165 - 0 to 165 -(n−1) is carried out. More specifically, when RS a decoding is carried out, by means of switches 162 - 0 to 162 -(n−1), multiplication coefficients {α av[j] } are output to multipliers 163 - 0 to 163 -(n−1), then multiplication of multiplication coefficients {α av[j] } and the data from registers 165 - 0 to 165 -(n−1) is carried out. On the other hand, when RS b decoding is carried out, by means of switches 162 - 0 to 162 -(n−1), multiplication coefficients {α bv[j] } are output to multipliers 163 - 0 to 163 -(n−1), then multiplication of multiplication coefficient {α bv[j] } and the data from registers 165 - 0 to 165 -(n−1) is performed.

For the RS b code, as an example with m=8, q=88, p=241, b=120, and L=15(t=8), one has the following equation (92): $$ Equation ⁢   ⁢ 92   { α bv ⁡ [ j ] } =   ⁢ { α bv ⁡ [ 0 ] , α bv ⁡ [ 1 ] , α bv ⁡ [ 2 ] , … ⁢   ⁢ α bv ⁡ [ t - 2 ] , α bv ⁡ [ t - 1 ] } =   ⁢ { α 241 × 88 × 255 , α 241 × 88 × 254 , α 241 × 88 × 253 , …   ⁢ α 241 × 88 × 249 , α 241 × 88 × 248 } ( 92 )

As the initial values of the registers, coefficients of said equation (87) are set as η˜η t−1 , and the values of η(α −pqk ) of said equation (91) corresponding to k=0, 1, 2 . . . can be derived successively in the same way.

Also, with the value of the numerator in said equation (91) is represented by equation (93): $$ Equation ⁢   ⁢ 93   α pq ⁡ ( b - 1 ) ⁢ ( - k ) ⁢ η ⁡ ( α - pqk ) =   ⁢ α pq ⁡ ( b - 1 ) ⁢ (   ⁢ k ) ⁢ { η t - 1 ⁢ α - pqk ⁡ ( t - 1 ) +   ⁢ η t - 2 ⁢ α - pqk ⁡ ( t - 2 ) + … + η 2 ⁢ α - pqk × 2 +   ⁢ η 1 ⁢ α - pqk + η 0 } =   ⁢ η t - 1 ⁢ α - pq ⁡ ( t + b - 2 ) ⁢ k +   ⁢ η t - 2 ⁢ α - pq ⁡ ( t + b - 3 ) ⁢ k + … +   ⁢ η 2 ⁢ α - pq ⁡ ( b + 1 ) ⁢ k + η 1 ⁢ α - pqbk + η 0 ⁢ α - pq ⁡ ( b - 1 ) ⁢ k ( 93 )

For the RS b code, as an example with m=8, q=88, p=241, b=120, and L=15(t=8), one has the following equation (94):

$$ Equation ⁢   ⁢ 94   { α bv ⁡ [ j ] } =   ⁢ { α bv ⁡ [ 0 ] , α bv ⁡ [ 1 ] , α bv ⁡ [ 2 ] , … ⁢   ⁢ α bv ⁡ [ t - 2 ] , α bv ⁡ [ t - 1 ] } =   ⁢ { α 241 × 88 × ( 255 - 119 ) , α 241 × 88 × ( 254 - 119 ) , α 241 × 88 × ( 253 - 119 ) ,   ⁢ … ⁢   ⁢ α 241 × 88 × ( 249 - 119 ) , α 241 × 88 × ( 248 - 119 ) } ( 94 )

The value of the numerator of said equation (91) are successively obtained. In addition, the following equation (95), as the relationship between derivative function σ′(x) of the polynomial of the aforementioned equation and polynomial σ odd (x) of the sum of the odd-number terms of the aforementioned position polynomial, can be used.

σ′( x )= xσ odd ( x )  Equation 95

Said equation (91) can be broken down to the following equation (96). $$ Equation ⁢   ⁢ 96   e k = α pq ⁡ ( b ⁢   ⁢ 1 ) ⁢ ( - k ) ⁢ η ⁡ ( α - pqk ) σ ′ ⁡ ( α - pqk ) = α pq ⁡ ( b - 1 ) ⁢ ( - k ) ⁢ η ⁡ ( α - pqk ) α - pqk ⁢ σ odd ⁡ ( α - pqk ) = α - pqbk ⁢ η ⁡ ( α - pqk ) σ odd ⁡ ( α - pqk ) ( 96 )

Because the value of the denominator can be derived simply in the process of detection of the error-position by said equation (88), the efficiency is even higher. The value of the numerator of said equation (96) is represented by the following equation (97). $$ Equation ⁢   ⁢ 97   α - pqbk ⁢ η ⁡ ( α - pqk ) =   ⁢ α - pqbk ⁢ { η t - 1 ⁢ α - pqk ⁡ ( t - 1 ) +   ⁢ η t - 2 ⁢ α - pqk ⁡ ( t - 2 ) + … ⁢   + η 2 ⁢ α - pqk × 2 +   ⁢ η 1 ⁢ α - pqk + η 0 } =   ⁢ η t - 1 ⁢ α - pq ⁡ ( t + b ⁢   ⁢ 1 ) ⁢ k + η t - 2 ⁢ α - pq ⁡ ( t + b - 2 ) ⁢ k + … +   ⁢ η 2 ⁢ α - pq ⁡ ( b + 2 ) ⁢ k + η 1 ⁢ α - pq ⁡ ( b + 1 ) ⁢ k + η 0 ⁢ α - pqbk ( 97 )

For the RS b code, as an example with m=8, q=88, p=241, b=120, and L=15(t=8), one has the following equation (98): $$ Equation ⁢   ⁢ 98   { α bv ⁡ [ j ] } =   ⁢ { α bv ⁡ [ 0 ] , α bv ⁡ [ 1 ] , α bv ⁡ [ 2 ] , … ⁢   ⁢ α bv ⁡ [ t - 2 ] , α bv ⁡ [ t - 1 ] } =   ⁢ { α 241 × 88 × ( 255 - 120 ) , α 241 × 88 × ( 254 - 120 ) ,   ⁢ α 241 × 88 × ( 253 - 120 ) , … ⁢   ⁢ α 241 × 88 × ( 249 - 120 ) ,   ⁢ α 241 × 88 × ( 248 - 120 ) } ( 98 )

The value of the numerator of said equation (96) are successively obtained.

As explained in the above, by means of RS coding/decoding device ( 101 ), by performing Galois field element transformation, it is possible to perform RS coding/decoding on a Galois field. As a result, it is possible to reduce the number of multipliers and the number of inverse element operation circuit, it is possible to reduce the scale of the device, and it is possible to cut the manufacturing cost.

This invention is not limited to the aforementioned embodiments.

For example, in the embodiments illustrated in FIGS. 3 , 4 , 7 , and 8 , switching of the Galois field multiplication coefficients corresponding to the various code generation polynomials is carried out alone. This is equivalent to switching of the multiplier with a fixed value (coefficient multiplier) . This type of coefficient multiplier can simply be realized as follows. For example, m by m matrix [xβ] is defined by the following equation (99) with respect to any z.

(β z+1 ) b =[x β](β z ) b   Equation 99

In said equation (99), [xβ] is derived from said field generation polynomial Gp b (x). More specifically, using B z,I ,z=m, I=0˜m−1 of said equation (55), the following equation (100) is established. $$ Equation ⁢   ⁢ 100   [ x ⁢   ⁢ β ] = ( B m , m - 1 1 0 … 0 0 0 B m , m ⁢   ⁢ 2 0 1 … 0 0 0     ⋮ ⋮     ⋮ B m , 3 0 0 … 1 0 0 B m , 2 0 0 … 0 1 0 B m , 1 0 0 … 0 0 1 B m , 0 0 0 … 0 0 0 ) ( 100 )

Consequently, the operation for the multiplication of certain fixed Galois field β d , that is, the matrix corresponding to the following equation (101), can be obtained as m by m matrix [xβ] d from said equation (100) equation 102. Consequently, when m=8, it can be realized by at most 10 of gates to 100 gates.

β z+d =β d ×β z   Equation 101

(β z+d ) b =[x β] d (β z ) b   Equation 102

On the other hand, when the input of the Galois field multiplier is not fixed, in the aforementioned case with m=8, 300-400 gates are needed. Consequently, when there are 2-3 RS codes with different corresponding Galois fields (that is, with different field generation polynomials), the efficiency is higher by switching the coefficient multipliers having fixed multiplication coefficients themselves as compared with the case of the switching of Galois field multiplication coefficients.

FIG. 9 is a diagram illustrating the embodiment of the constitution in which switching of the set of Galois field multiplication coefficients shown in FIG. 1 is realized by switching of the set of coefficient multipliers (the number of the RS codes that can be handled is 2). As shown in FIG. 9 , the RS coding/decoding device has RS coding/decoding core unit 112 , multiplier 113 , switches 114 , 118 , 121 , inverse element operation circuit 115 , input-side transformation circuit 116 b coefficient multipliers 171 a, 171 b, and output-side transformation circuit 119 b.

When the fixed Galois field multiplier itself is switched, the circuit constitution shown in FIGS. 3 , 4 , 7 , and 8 does not have much advantage over the conventional constitution with respect to the circuit scale. However, for the circuit constitution shown in FIGS. 5 and 6 , because the input of the Galois field multiplier is not fixed, the scheme of this embodiment is preferred with respect to the circuit scale as compared with the conventional constitution with the number of the Galois field multipliers equal to the number of the RS codes (FIGS. 14 and 15 ).

In the aforementioned embodiment, for the RS coding/decoding device of the RS code (RS a code) defined over the originally present first Galois field (GF a (2 m )), the topic is how to construct, at a high efficiency, the RS coding/decoding device of the RS code (RS b code) defined over the second Galois field GF b (2 m ).Because the purpose is to form an RS coding/decoding device that can handle two RS codes, it is also possible to make use of a common Galois field multiplier as the third Galois field GF c (2 m ) different from said Galois field GF a (2 m ) and GF b (2 m ). FIG. 10 is a diagram illustrating an example of this constitution.

As shown in FIG. 10 , in this RS coding/decoding device, there are the following parts: RS coding/decoding core unit 112 , input-side transformation circuits 116 a, 116 b, multiplier 113 , inverse element operation circuit 115 , multipliers 118 b, 118 c, output-side transformation circuits 119 a, 119 b, and switches 118 , 121 , 182 [sic].

In addition, in the aforementioned embodiment, an explanation was made with regard to the correction power for an RS a code identical to that of RS b code. It is clear that when there is a circuit matched with the side having a higher correction power, the other side may make use of said side in this constitution. That is, a condition for deriving the RS a code and RS b code in this scheme is that their field generation polynomials have the same order.

In the aforementioned embodiment of RS coding, the Euclidean decoding method was used in the explanation. However, this invention is not limited to this scheme. In this respect, because the fact that the series after the Galois field transformation is equivalent to the RS code (Goppa code) corresponding to the code generation polynomial of said equation ( 27 ) is generally proven, the well-known RS decoding method (Goppa decoding method or BCH decoding method in a higher class) may be applied.

As explained in the above, for the Reed-Solomon coding device and method of this invention, by performing the element transformation of the Galois field, it is possible to perform RS coding on a single Galois field. As a result, it is possible to reduce the number of multipliers and the number of inverse element operation circuit [parts], it is possible to reduce the scale of the device, and it is possible to cut the manufacturing cost.

Also, in the Reed-Solomon coding device and method of this invention, by performing the element transformation of the Galois field, it is possible to perform decoding of the RS coding data on a single Galois field. As a result, it is possible to reduce the number of multipliers and the number of inverse element operation circuit [parts], it is possible to reduce the scale of the device, and it is possible to cut the manufacturing cost.

Claims

1. A type of Reed-Solomon coding device that can handle multiple RS (Reed-Solomon) codes using different field generation polynomials, comprising:means for storing multiple multiplication coefficient sets corresponding to multiple code-forming polynomials; switching means for selecting one of said coefficient sets; a Galois field transformation means that transforms the input data to the data of a prescribed Galois field; a coding means that performs coding processing using a selected multiplication coefficient set for the aforementioned transformed data by means of the aforementioned Galois field after transformation; and a Galois field inverse transformation means that undertakes inverse transformation of the coded data of the aforementioned Galois field to a Galois field before transformation.

2. The Reed-Solomon coding device described in claim 1, wherein the aforementioned coding means has a multiplier corresponding to the aforementioned Galois field after transformation.

3. The Reed-Solomon coding device described in claim 1, wherein the aforementioned multiple RS codes are RSa codes and RSb codes using different field generation polynomials;the coding symbols are Galois fields GFa(2m) and GFb(2m) extended based on m-th order field generation polynomials GPa(x) and GPb(x) that are different from each other on Galois field GF(2), respectively; for α as the root of said Gpa(x) and as the primitive element of said GFa(2m) and for β as the root of said Gpb(x) and as the primitive element of said GFb(2m), the following equation (1) is established; said RSb code has power of t-symbol error correction, and its code forming polynomial Gcb(x) is represented by the following equation (2); when the aforementioned input data are coded by said RSb code, said Galois field transformation means transforms the Galois field of the aforementioned input data from said Galois field GFb(2m) into said Galois field GFa(2m); the aforementioned coding means performs coding corresponding to the following equation (3) as a polynomial, which transforms said code generation polynomial Gcb(x) to said Galois field GFa(2m); and the aforementioned Galois field inverse transformation means undertakes inverse transformation of the aforementioned Galois field of coded data from said Galois field GFa(2m) into said Galois field GFb(2m); Gpb(αp)=0  Equation 1 Equation⁢ ⁢2 Gcb⁡(x)=∏j=0L⁢(x+βq⁡(b+j)),L=2⁢t-1, ⁢or⁢ ⁢2⁢t Equation⁢ ⁢3 Gcba⁡(x)=∏j=0L⁢(x+αpq⁡(b+j)),L=2⁢t-1, ⁢or⁢ ⁢2⁢t.

4. The Reed-Solomon coding device described in claim 1, whereinwith the transposed matrix represented as ( . . . )T, when m values among the 2m input/output relationships are as follows: with respect to m-bit input (00 . . . 0001)T, m-bit output A0=(00 . . . 001)T is performed; with respect to m-bit input (00 . . . 0010)T, m-bit output A1=(A1,m−1, A1,m−2, . . . A1,0)T is performed; with respect to m-bit input, (00 . . . 0100)T m-bit output A2=(A2,m−1, A2,m−2, . . . A2,0)T is performed; with respect to m-bit input (01 . . . 0000)T, m-bit output Am−2=(Am−2,m−1, Am−2,m−2, . . . Am−2,0)T is performed; with respect to m-bit input (10 . . . 0000)T, m-bit output Am−1=(Am−1,m−1, Am−1,m−2, . . . Am−1,0)T is performed; with m by m matrix [Hba] being defined by the following equation (4); and the aforementioned Galois field transformation means performs operation processing corresponding to the following equation (5) with respect to said m-bit input data Db-in to generate m-bit output data Da-out; [Hba]=(Am−1Am−2 . . . A2A1A0)  Equation 4 Da-out=[Hba]×Db-in  Equation 5.

5. The Reed-Solomon coding device described in claim 4, wherein the aforementioned Galois field inverse transformation means performs operation processing corresponding to the following equation (6) to generate m-bit output data Db-out when the inverse matrix of said matrix [Hba] is [Hab];Db-out=[Hab]×Da-in  Equation 6.

6. A type of Reed-Solomon decoding device, that can handle multiple RS codes using different field generation polynomials, comprising:means for storing multiple multiplication coefficient sets corresponding to multiple code-forming polynomials; switching means for selecting one of said coefficient sets; a Galois field transformation means that transforms the input coded data into the coded dat of the prescribed Galois field; a decoding means that performs decoding processing using a selected multiplication coefficient set of the aforementioned transformed coded data by means of the aforementioned Galois field after transformation; and a Galois field inverse transformation means that undertakes inverse transformation of the decoded data of the aforementioned Galois field to a Galois field before transformation.

7. The Reed-Solomon decoding device described in claim 6, wherein the aforementioned Galois field transformation means has a multiplier corresponding to the aforementioned Galois field after transformation.

8. The Reed-Solomon decoding device described in claim 6, wherein the aforementioned multiple RS codes are RSa codes and RSb codes using different field generation polynomials;the coding symbols are Galois fields GFa(2m) and GFb(2m) extended based on m-th order field generation polynomials Gpa(x) and Gpb(x), which are different from each other, on Galois field GF(2), respectively; for α as the root of said GPa(x) and as the primitive element of said GFa(2m) and for β as the root of said Gpb(x) and as the primitive element of said GFb(2m), the following equation (7) is established; said RSb code has power of t-symbol error correction, and its code generation polynomial Gcb(x) is represented by the following equation (8); when the aforementioned input coded data are decoded; said Galois field transformation means transforms the Galois field of the aforementioned coded data from said Galois field GFb(2m) into said Galois field GFa(2m); the aforementioned decoding means performs decoding corresponding to the following equation (9) as a polynomial that transforms said code generation polynomial Gcb(x) into said Galois field GFa(2m); and the aforementioned Galois field inverse transformation means undertakes transformation of the aforementioned Galois field of decoded data from said Galois field GFa(2m) into said Galois field GFb(2m); Gpb(αp)=0  Equation 7 Equation⁢ ⁢ ⁢8 Gcb⁡(x)=∏j=0L⁢(x+βq⁡(b+j)),L=2⁢t-1, ⁢or⁢ ⁢2⁢t Equation⁢ ⁢9 Gcba⁡(x)=∏j=0L⁢(x+αpq⁡(b+j)),L=2⁢t-1, ⁢or⁢ ⁢2⁢t.

9. The Reed-Solomon decoding device described in claim 6 wherein with the transposed matrix represented as ( . . . )T, when m values among the 2m input/output relationships are as follows:with respect to m-bit input (00 . . . 0001)T, m-bit output A0=(00 . . . 001)T is performed; with respect to m-bit input (00 . . . 0001)T, m-bit output A1=(A1,m−1, A1,m−2, . . . A1,0)T is performed; with respect to m-bit input (00 . . . 0100)T, m-bit output A2=(A2,m−1, A2,m−2, . . . A2,0)T is performed; with respect to m-bit input (01 . . . 0000)T, m-bit output Am−2=(Am−2,m−1, Am−2, m−2, . . . Am−2,0)T is performed; with respect to m-bit input (10 . . . 0000)T, m-bit output Am−1=(Am−1,m−1, Am−1,m−2, . . . Am−1,0)T is performed; with m by m matrix [Hba] being defined by following equation (10); with the aforementioned Galois field transformation means performing operation processing corresponding to the following equation (11) with respect to said m-bit input data Db-in to generate m-bit output data Da-out; [Hba]=(Am−1Am=2 . . . A2A1A0)  Equation 10 Da-out=[Hba]×Db-in  Equation 11.

10. The Reed-Solomon coding device described in claim 9, wherein the aforementioned Galois field inverse transformation meansperforms operation processing corresponding to the following equation (12) to generate m-bit output data Db-out when the inverse matrix of said matrix [Hba] is [Hab]; Db-out=[Hab]×Da-in  Equation 12.

11. A Reed-Solomon coding method, comprising in a Reed-Solomon decoding method that can handle multiple RS codes using different field generation polynomials, the steps of:input data is transformed into data of a prescribed Galois field; for the aforementioned transformed data, coding processing is carried out by means of the aforementioned Galois field after transformation; coded data of the aforementioned Galois field is inverse transformed into data of a Galois field before the aforementioned transformation; and wherein the aforementioned multiple RS codes are RSa codes and RSb codes using different field generation polynomials;the coding symbols are Galois fields GFa(2m) and GFb(2m) extended based on m-th order field generation polynomials Gpa(x) and Gpb(x) which are different from each other, on Galois field GF(2), respectively; for α as the root of said Gpa(x) and as the primitive element of said GFa(2m) and for β as the root of said Gpb(x) and as the primitive element of said GFb(2m), the following equation (13) is established; said RSb code has power of t-symbol error correction, and its code generation polynomial Gcb(x) is represented by the following equation (14); when the aforementioned input data are coded by said RSb code, the Galois field of the aforementioned input data is transformed from said Galois field GFb(2m) into said Galois field GFa(2m); the aforementioned coding is performed corresponding to the following equation (15) as a polynomial that transforms said code generation polynomial Gcb(x) into said Galois field GFa(2m); and the aforementioned Galois field of the coded data is inverse transformed from said Galois field GFa(2m) into said Galois field GFb(2m), Gpb(αp)=0  Equation 13 Equation⁢ ⁢ ⁢14 Gcb⁡(x)=∏j=0L⁢(x+βq⁡(b+j)),L=2⁢t-1, ⁢or⁢ ⁢2⁢t(14)Equation⁢ ⁢15 Gcba⁡(x)=∏j=0L⁢(x+αpq⁡(b+j)),L=2⁢t-1, ⁢or⁢ ⁢2⁢t.(15)

12. A Reed-Solomon coding method, comprising in the Reed-Solomon decoding method that can handle multiple RS codes using different field generation polynomials, the steps of:the input data are transformed into the data of a prescribed Galois field, for the aforementioned transformed data, coding processing is carried out by means of the aforementioned Galois field after transformation; the Galois field of the aforementioned coded data is inverse transformed into the Galois field before the aforementioned transformation; and wherein with the transposed matrix represented as ( . . . )T, when m values among the 2m transformation relationships are as follows:with respect to m-bit input (00 . . . 0001)T, m-bit output A0=(00 . . . 001)T is performed; with respect to m-bit input (00 . . . 0010)T, m-bit output A1=(A1,m−1, A1,m−2, . . . A1,0T is performed; with respect 59 m-bit input (00 . . . 0100)T, m-bit output A2(A2,m−1, A2,m−2, . . . A2,0)T is performed; with respect to m-bit input (00 . . . 0100)T, m-bit output Am−2=(Am−2,m−1, Am−2,m−2, . . . Am−2,0)T is performed; with respect to m-bit input (10 . . . 0000)T, m-bit output Am−1=(Am−1,m−1, Am−1,m−2, . . . Am−1,0)T is performed; and m by m matrix [Hba] is defined by the following equation (16), the aforementioned Galois field transformation of the input data is performed by carrying out operation processing corresponding to the following equation (17) with respect to said m-bit input data Db-in to generate m-bit output data Da-out;  [Hba]=(Am−1Am−2 . . . A2A1A0)  Equation 16Da-out=[Hba]×Db-in  Equation 17.

13. The Reed-Solomon coding method described in claim 12, wherein the aforementioned Galois field inverse transformation is performed by:carrying out operation processing corresponding to the following equation (18) to generate m-bit output data Db-out when the inverse matrix of said matrix [Hba] is [Hab]; Db-out=[Hab]×Da-in  Equation 18.