Patent Application
20080074205
A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
Referring now to the drawings, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
Referring to
A peripheral clock output 114 may be available and configurable for a desired clock frequency for other integrated circuit digital devices (not shown). This feature saves cost and printed circuit board space by eliminating the need for additional clock sources and/or clock drivers for the other integrated circuit digital devices of the electronic system (not shown).
The digital device 102 may comprise an oscillator/buffer 104, a frequency divider 108, an internal clock oscillator 110, a clock source selection switch 124, and logic circuits 106. The oscillator/buffer 104 may be coupled to an external crystal 112 or an external clock source 120 at input 118, or to an internal clock oscillator 126 with the clock source selection switch 124. The oscillator/buffer 104 may, acting as a crystal oscillator, generate a clock signal at a frequency determined by the external crystal 112, or as a clock buffer when coupled to either the external clock source 120 or the internal clock oscillator 126 through the clock source selection switch 124.
Switching between the external clock source 120, the external crystal 112, or the internal clock oscillator 110 may be done synchronously so as not to produce any undesired “glitches” that could be mistaken for a clock signal. A output 122 from the oscillator/buffer 104 may be coupled to a clock divider 108, e.g., divide by a positive integer value. The output of the clock divider 108 may be coupled to a peripheral clock output 114 and is available for use as another clock signal to the other integrated circuit devices (not shown). The divide ratio of the clock divider 108 may be programmable. The clock divider 108 may also be used as a pass through circuit that does not change the frequency of the clock the output 122. It is contemplated and with the scope of this disclosure that the logic 106 may go into a standby/sleep mode without affecting operation of the clock generation circuits described hereinabove so that a clock signal may be present at the output 114 for use by the other integrated circuit devices (not shown).
Referring to
The digital device 102a may comprise a oscillator/buffer 104, a first frequency divider 208, an internal clock oscillator 110, a clock source selection switch 124, a second frequency divider 216, a third frequency divider 209, a clock source multiplexer 210, and logic circuits 106. The oscillator/buffer 104 may be coupled to an external crystal 112, an external clock source 120 or an internal clock oscillator 126 with the clock source selection switch 124. The oscillator/buffer 104 may, acting as a crystal oscillator, generate a clock signal at a frequency determined by the external crystal 112, or as a clock buffer when coupled to either the external clock source 120 or the internal clock oscillator 126 through the clock source selection switch 124.
The oscillator/buffer 104 may provide a clock signal 122 that may be coupled to the logic 106 and an input of the clock multiplexer 210. Another input of the clock multiplexer 210 may be coupled to an output of the second frequency divider 216. The clock multiplexer 210 may thereby be used to select a clock source to be divided by the first frequency divider 208, and to provide this frequency divided clock source at the peripheral clock output 114 for use as another clock signal to the other integrated circuit devices (not shown). The third frequency divider 209 maybe used to provide another frequency divided clock source at the peripheral clock output 214 and may be used as an additional clock signal to yet other integrated circuit devices (not shown). It is contemplated and within the scope of this disclosure that a plurality of frequency dividers may be implemented into the digital device 102a, wherein the outputs from each of the plurality of frequency dividers may be used to provide clock signals at the same or different frequencies and for supporting a variety of peripherals devices (not shown), e.g., Ethernet interface, wireless bridge, USB, etc. Thus, cost and space savings of a reduction of oscillator components, e.g., external crystals may be achieved.
The first frequency divider 208 and/or third frequency divider 209 may also be used as a pass through circuit(s) that does not change the frequency of the clock at the output 122. Similarly, the second frequency divider 216 may also be used as a pass through circuit that does not divide the clock frequency received at the input 220.
Switching between the external clock source 120 or crystal 112 and the internal clock oscillator 110 may be done synchronously so as not to produce any undesired “glitches” that could be mistaken for a clock signal. Likewise, switching between the clock signal 122 and the output of the second frequency divider 216 may be done synchronously so as not to produce any undesired “glitches” that could be mistaken for a clock signal.
The frequency divide ratio of the first frequency divider 208, third frequency divider 209, and/or second frequency divider 216 may be programmable and divide frequencies by any positive integer value. The output of the first frequency divider 208 may be coupled to the peripheral clock output 114 and is available for use as a lower frequency clock signal to the other integrated circuit devices (not shown). The output of the third frequency divider 209 may be coupled to the peripheral clock output 214 and is available for use as a lower frequency clock signal to still other integrated circuit devices (not shown) that may require a different clock frequency that the clock available at the peripheral clock output 114.
Referring to
A peripheral clock output 114 may be available and configurable for a desired clock frequency for other integrated circuit digital devices (not shown). This feature saves cost and printed circuit board space by eliminating the need for additional clock sources and/or clock drivers for the other integrated circuit digital devices of the electronic system (not shown).
The digital device 102 may comprise an oscillator/buffer 104, and logic circuits 106. The oscillator/buffer 104 may be coupled to an external crystal 112 or an external clock source 120 at input 118. The oscillator/buffer 104 may, acting as a crystal oscillator, generate a clock signal at a frequency determined by the external crystal 112, or as a clock buffer when coupled to the external clock source 120.
Switching between the external clock source 120 or the external crystal 112 may be done synchronously so as not to produce any undesired “glitches” that could be mistaken for a clock signal. It is contemplated and with the scope of this disclosure that the logic 106 may go into a standby/sleep mode without affecting operation of the clock generation circuits described hereinabove so that a clock signal may be present at the output 114 for use by the other integrated circuit devices (not shown).
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.
This application claims priority to commonly owned U.S. Provisional Patent Application Ser. No. 60/827,075; filed Sep. 27, 2006; entitled “Reference Clock Out Feature on a Digital Device Peripheral Function Pin” by Mei-Ling Chen, Igor Wojewoda and Gaurang Kavaiya; and is hereby incorporated by reference herein for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 60827075 | Sep 2006 | US |
