Embodiments of the invention relate to a reference current circuit for providing a temperature compensated reference current.
Conventional bandgap circuits generate a reference current or a reference voltage by combining two voltage drops, the first voltage drop having a positive temperature coefficient and the second voltage drop having a negative temperature coefficient, so that the resulting reference current or reference voltage is substantially temperature independent. Such bandgap circuits may comprise bipolar transistors and the voltage drops are the base-emitter voltage drops (VBE). Such bandgap circuits may be used for providing to electronic devices a desired reference current or a desired reference voltage. The bandgap circuit may be provided as a separate circuit element or may be formed together with the electronic device. For example, the bandgap circuit may be formed using the SiGe:C (silicon germanium) technology. Implementing the bandgap circuit in this technology uses silicon germanium (SiGe) transistors having a characteristic base-emitter voltage drop (VBE) of about 0.8 V. Such bandgap circuits will not operate below 2V.
However, new trends in electronics and semiconductor technology may require further reduction in power consumption so that devices may be required to operate at voltages in the range below 2V, e.g., between 1V and 1.5V. The above described conventional bandgap circuits are designed to provide supply voltages down to 2V but not down to 1V to 1.5V so that a redesign of such conventional bandgap circuits would be required. For example, since bandgap circuits comprise series-connected BE-junctions, a semiconductor technology using silicon germanium transistors offers base-emitter voltage drops of around 0.8V. With two silicon germanium transistors connected in series a voltage drop of 1.6 V is applied to the circuit which requires supply voltages above at least 1.6V, in general above 2V. Thus, any redesign of such a conventional bandgap circuit would require a new design approach that uses different materials having, e.g., smaller bandgap voltages as silicon germanium. However, changing the technology is expensive and semiconductor materials with a smaller voltage drop may be very expensive in the manufacturing process.
Embodiments of the invention provide a reference current circuit for providing a temperature compensated reference current.
With reference to the accompanying figures embodiments of a reference current circuit and embodiments of a low power bias circuit using the same will be described.
As mentioned above, new trends to reduce the power consumption may require the design of a bias network able to operate at voltages as low as, e.g., 1V to 1.5V. There is a need to avoid a redesign of the conventional bandgap circuits and the associated problems of high expenses and difficulties when using different semiconductor materials with a smaller voltage drop. Therefore, embodiments of the invention relate to a reference current circuit which avoids series connected BE-junctions (as used in conventional bandgap circuits) thereby allowing good performance down to, e.g., 1V to 1.5V. Therefore, embodiments of the invention allow maintaining the semiconductor manufacturing technology, e.g., using silicon-germanium transistors, while changing the design of the circuit by using parallel base-emitter voltage drops instead of series base-emitter voltage drops. Embodiments of the invention offer a good supply rejection together with a good temperature stability. Embodiments of the invention provide a temperature-compensated voltage independent current source and low voltage low power bias networks. Such current sources or networks may be used for low noise amplifiers that operate at low power, for example for GPS (global positioning system) or DVB (digital video broadcast).
The input current Iin may have a temperature coefficient and the reference current circuit 100 is configured to compensate this temperature coefficient in order to provide a reference current Iout showing no temperature dependence. The input current Iin may be provided by a Widlar current mirror, a Nagata current mirror (see
As can be seen from
To compensate for the temperature dependency of the input current Iin the reference current circuit 100 is dimensioned as shown below. For the following calculations the currents that flow into the base terminals of the transistors are neglected. Further, ICQ4=collector current of Q4, ICQ5=collector current of Q5, ISQ4=saturation current of Q4, ISQ5=saturation current of Q5.follows:
For U1, neglecting the base currents:
But U1 also is:
Differentiating both sides and assuming TCRs=0:
For full temperature compensations
The calculated values may be used as a starting point for optimizing the circuit in a circuit simulator.
The peaking current mirror circuit 200 may be a Nagata current mirror. The peaking current mirror circuit 200 comprises an input 203 configured to receive the start current 201 and an output 204 configured to provide the mirror current 202 as the input current Iin to the reference current circuit 100. The peaking current mirror circuit 200 further comprises a first PNP bipolar transistor Q2 having a base terminal 206, an emitter terminal 207 and a collector terminal 208, a second PNP bipolar transistor Q3 having a base terminal 210, an emitter terminal 211 and a collector terminal 212 with an area ratio of the two transistors Q3/Q1=M. The input 203 is directly connected to the base terminal 206 of the first PNP bipolar transistor Q2 and is connected via a resistor R2 to the collector terminal 208 of the first PNP bipolar transistor Q2 and the base terminal 210 of the second PNP bipolar transistor Q3. The output 204 is connected to the collector terminal 212 of the second PNP bipolar transistor Q3. A supply node 213 is connected to the emitter terminals 207, 211 of both PNP bipolar transistors Q2, Q3.
The reference current circuit 100 is adapted to compensate the temperature coefficient of the mirror current 202, wherein the temperature coefficient is represented by the thermal voltage φT=kT/q. The temperature coefficient of the mirror current 202 is approximately inverse proportional to a squared temperature. The reference current circuit 100 is adapted to compensate this temperature coefficient by applying a transformation with a squared temperature.
To provide the start current 201 for the peaking current mirror circuit 200 the low power bias circuit 300 comprises an enabling circuit 400 having an enabling line 401 configured to receive a logic enable signal. The enabling circuit 400 further comprises an output 402 configured to provide the start current 201. The enabling circuit 400 further comprises a NPN bipolar transistor Q1 having a base terminal 404, an emitter terminal 405 and a collector terminal 406. The enabling line 401 is connected via a parallel connection of a first resistor R1 and a capacitor C1 to the base terminal 404 of the NPN bipolar transistor Q1. The output 402 is connected via a second resistor R3 to the collector terminal 406 of the NPN bipolar transistor Q1. The emitter terminal 405 of the NPN bipolar transistor Q1 is connected to the reference potential 110. The bipolar transistor Q3 is configured to provide the start current 201 when the enabling line 401 receives the logic enable signal. The second resistor R3 is a start current setting resistor and is configured to set the start current 201.
One embodiment of the invention may comprise a Widlar current mirror. The optional Widlar current mirror 500 comprises an input 502 configured to receive the reference current Iout from the reference current circuit 100 and an output 503 configured to provide the output current 501. The output 503 may be connected to an output port. The Widlar current mirror 500 further comprises a first PNP bipolar transistor Q6 having a base terminal 505, an emitter terminal 506 and a collector terminal 507, and a second PNP bipolar transistor Q7 having a base terminal 509, an emitter terminal 510 and a collector terminal 511. The input 502 is connected to the collector terminal 507 of the first PNP bipolar transistor Q6, to the base terminal 505 of the PNP first bipolar transistor Q6 and to the base terminal 509 of the second PNP bipolar transistor Q7. The output 503 is connected to the collector terminal 511 of the second PNP bipolar transistor Q7. The supply node 213 is connected to the emitter terminal 506 of the first PNP bipolar transistor Q6 and to the emitter terminal 510 of the second PNP bipolar transistor Q7. The supply node 213 may be the same as the one for the peaking current mirror circuit 200 and may be connected to a supply voltage port 214 providing a predefined supply voltage Vcc.
The low power bias circuit 300 is configured to operate at supply voltages in the range of 1 V to 2 V. However, the low power bias circuit 300 may also operate with supply voltages above 2 V. The low power bias circuit 300 is designed to replace conventional bandgap circuits implemented in the same technology, e.g., using SiGe:C transistors and allows operation at voltages smaller than the voltage provided by a conventional bandgap circuit. The reference current circuit 100 is configured to provide a reference current Iout that is independent of the supply voltage and the reference voltage. The peaking current mirror circuit 200 offers a good supply rejection and the reference current mirror 100 is configured to compensate the temperature coefficient of the first one.
The following calculations will describe a possible approach for dimensioning the reference current circuit (temperature-compensating mirror 100) in
The input current of the temperature-compensating mirror is the collector current of transistor Q3 and is a function of the base-emitter voltage VBEQ3 and the temperature:
where ISQ3 is the saturation current of Q3 and φT=kT/q is the thermal voltage. Neglecting the base currents (for the sake of clarity):
Dividing (1) by (2) results in:
The peak value is reached when
(5) can be used to calculate R2 for a given collector current:
R3 can be calculated as follows:
The temperature coefficient of ICQ3 is:
In case of TCR2 and TCR3=0:
For U1, neglecting the base currents:
But U1 also is:
Differentiating both sides and assuming TCRs=0:
For full temperature compensations
The calculated values can be used as a starting point for optimizing the circuit in a circuit simulator.
Although embodiments of the invention were described on the basis of NPN bipolar transistors Q1, Q4, Q5, and Q8 and PNP bipolar transistors Q2, Q3, Q6 and Q7 for a negative logic the same functionality can be implemented by replacing the NPN transistors by PNP transistors and PNP transistors by NPN transistors.
Although embodiments of the invention were described on the basis of bipolar transistors, it is noted that the invention is not limited to such embodiments. Instead of bipolar transistors also MOSFETs, JFETs (junction field-effect transistors), MSFETs (metal semiconductor field-effect transistors), HEMTs (high electron mobility transistors), HSFETs (hetero structure FET), MODFETs (modulation-doped field-effect transistors), IGBTs (insulated gate bipolar transistors), HJBTs (hetero junction bipolar transistors) or other kinds of transistors may be used.