Reference current/voltage generator having reduced sensitivity to variations in power supply voltage and temperature

Abstract

A reference current/voltage gnereator is insensitive to variations in power supply voltage and temperature. The operational parameters of matched current mirror transistors of the generator are effectively equalized by an auxiliary bias amplifier, whose transistors are matched with and connected to the current mirror transistors of the generator in such a manner as to maintain the same electrical parameters in each of the current mirror legs of the current generator, irrespective of variations in supply voltage. Temperature insensitivity is achieved by making the output current mirror a current that is the sum of two currents whose current paths complementary temperature coefficients.

Description

FIELD OF THE INVENTION

The present invention relates in general to circuits employed for the generation of reference currents and/or reference voltages, and is particularly directed to a new and improved multi transistor-configured reference current and voltage generator, that is effectively insensitive to variations in power supply voltage and temperature.

BACKGROUND OF THE INVENTION

FIGS. 1 , 2 and 3 respectively depict conventional bipolar, CMOS and BiCMOS current mirror transistor circuits, that are widely used throughout the electronics industry to generate a reference current I OUT , that is to be supplied to one or more signal processing circuits of an integrated circuit architecture. ‘Ideally’, this reference current I OUT may be defined by equation (1) as: $$ I OUT = KT q * ln ⁡ ( N ) R1 = V T * ln ⁡ ( N ) R1 ( 1 )

Using the bipolar transistor configuration of FIG. 1 as a representative example of the set of three current generator circuits, the ideal value for its output reference current I OUT is based upon the assumption that the current mirror transistors in the two legs of the generator are perfectly matched and that each of the bipolar transistors Q 1 /Q 2 , Q 4 /Q 5 has infinite h fe or beta. Namely, if current mirror transistor pair Q 1 and Q 2 are perfectly matched, the collector current through transistor Q 1 in one leg of the circuit is equal to the collector current flowing through transistor Q 2 in the opposing leg. Also, if the current mirror transistor pair Q 4 and Q 5 have infinite h fe or beta, the emitter current of transistor Q 4 will be the same as the emitter current of Q 5 , which equals the current through resistor R 1 . The relationship between these currents is summarized in equation (2) as follows:

I C(Q1) =I C(Q2) =I C(Q4) =I C(Q5) =I E(Q4) =I E(Q5) =I RI =I OUT   (2)

In addition, the voltage drop V BE(Q 4) across the base-emitter junction of transistor Q 4 will equal the voltage drop V BE(Q5) , plus the voltage drop across resistor R 1 , as set forth in equation (3) as follows:

V BE(Q4) =V BE(Q5) +I OUT *R 1   (3).

It is well known that the V BE of a bipolar transistor is equal to the natural log (ln) of the ratio of its collector-emitter current (I) to the saturation current (Is), as set forth in equation (4). $$ V BE = KT q * ln ⁡ ( I I s ) = KT q * ln ⁡ ( I EmitterArea ⁡ ( Q5 ) * Js ⁡ ( Q5 ) ) = V T * ln ⁡ ( I EmitterArea ⁡ ( Q5 ) * Js ⁡ ( Q5 ) ) ( 4 )

The saturation current (Is) can be rewritten as the emitter area of the transistor multiplied by the saturation current per unit area, or the saturation current density (Js), as also shown in equation (4). Substituting this expression for V BE into equation (3) yields equation (5), as follows: $$ V T * ln ⁡ ( I EmitterArea ⁡ ( Q4 ) * Js ⁡ ( Q4 ) ) = V T * ln ⁡ ( I EmitterArea ⁡ ( Q5 ) ⁢ Js ⁡ ( Q5 ) ) + I * R1 ( 5 )

The saturation current densities for transistors with the same doping profiles, formed in the same substrate, and using the same processing steps, will match each other extremely well. As a consequence, it may be inferred that the saturation current density of the transistor Q 4 of the current generator of FIG. 1 equals the saturation current density of transistor Q 5 , as defined in equation (6).

Js (Q 4 )= Js (Q 5 )= Js (npn)  (6)

Equation (7), set forth below, shows that current mirror transistors Q 4 and Q 5 of the current generator of FIG. 1 are designed such that the ratio of the emitter area of transistor Q 5 to the emitter area of transistor Q 4 is set to a known constant N, defined in equation (7) as:

N=EmitterArea(Q 5 )/EmitterArea(Q 4 )  (7)

Solving equation (5) for I and substituting into equations (6) and (7) yields equation (8), as follows:

$$ I = V T * ln ⁢   ⁢ ( I * EmitterArea ⁡ ( Q5 ) * Js ⁡ ( Q5 ) I * EmitterArea ⁡ ( Q4 ) * Js ⁡ ( Q4 ) ) R1 = V T * ln ⁡ ( N ) R1 ( 8 )

The sensitivity of a circuit to changes in its power supply voltage is called power supply rejection (PSR). If a circuit had infinite PSR, the output of that circuit would not be affected by changes in the power supply voltage. Although equation (8) implies that the reference current I OUT generated by the current mirror transistor circuits of the current generator architecture of FIGS. 1 through 3 is independent of its power supply voltage Vcc, this equation assumes infinite h fe and ‘perfectly matched’ current mirror transistors. In a practical circuit, however, the early voltage effect, shown in the collector current vs. collector-emitter voltage characteristic of FIG. 4 , will cause mismatches in the current mirrors.

In the bipolar configuration of FIG. 1 , for example, the early voltages of the two current mirror transistors Q 1 and Q 2 will cause a mismatch in their collector currents, since the collector-emitter voltage V CE of transistor Q 1 is not equal to the collector-emitter voltage V CE of transistor Q 2 . This difference in collector-emitter voltages is due to the fact that the collector-emitter voltage (V CE ) of transistor Q 1 equals the power supply voltage rail differential (Vcc−GND) minus the base-emitter voltage (V BE ) to GND rail differential (e.g., approximately 0.7V) of diode-connected transistor Q 4 .

For a Vcc=5V power supply, therefore, the V CE of transistor Q 1 would be approximately equal to (5.0-0.7=) 4.3 volts. Since, however, its associated current mirror transistor Q 2 is diode-connected, the V CE of transistor Q 2 equals its V BE (0.7V), or about one-sixth of that of transistor Q 1 . This mismatch in the V CE voltages of the current mirror transistors Q 1 and Q 2 results in a mismatch in their collector currents (even though the V BE voltages of Q 1 and Q 2 are identical).

Such mismatches in the current mirrors will cause the reference current I OUT to deviate from the ideal value set forth in Equation (8). This problem is made worse by the fact that the mismatch in the current mirror transistors will change as the power supply voltage varies. Therefore, due to the early voltage effect alone, the reference current I OUT generated by the circuits shown in FIGS. 1 through 3 is not independent of power supply voltage variation.

This can be a significant problem in low voltage applications having reduced power supply ‘headroom’, where high power supply rejection is required. Such headroom limitations are becoming increasingly common as the industry continues to use lower and lower power supply voltages. To solve this problem in a bipolar circuit of the type shown in FIG. 1 , it has been proposed to couple an auxiliary bias amplifier in circuit with one of the legs of the current generator, as diagrammatically illustrated in FIG. 5 , and as described, for example, in an article by M. Gunawan et al, entitled: “A Curvature-Corrected Low Voltage Bandgap Reference”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 6, June 1993, pp 667-670, and also in an article by H. Nauta et al, entitled: “New Class of High-Performance PTAT Current Sources,” Electronics Letters, Apr. 25, 1985, Vol. No. 9, pp 384-386.

In the bipolar scheme of FIG. 5 , the voltages across associated transistors of the two current mirror legs of the current generator are effectively equalized by means of an auxiliary bias amplifier 50 , formed of a current mirror PNP transistor Q 51 and a V CE -controlling NPN transistor Q 55 . These two bias amplifier transistors have their collector-emitter current paths connected in parallel with those of transistor pairs Q 52 /Q 53 and Q 56 /Q 57 , of the two current mirror legs that are connected between the power supply rails (Vcc and ground).

The first polarity (PNP) transistor Q 51 of the auxiliary bias amplifier 50 is connected in a diode configuration (having its collector connected to its base), with the base electrode of PNP transistor Q 51 being connected in common to the bases of PNP transistors Q 52 and Q 53 , and Q 54 with which auxiliary transistor Q 51 forms a current mirror. The base of the second polarity (NPN) transistor Q 55 of the auxiliary bias amplifier is coupled to the collector current path of that leg of the current generator containing PNP current mirror transistor Q 52 and NPN current mirror transistor Q 56 . The PNP transistor Q 51 of the bias amplifier 50 is matched with PNP current mirror transistors Q 52 and Q 53 , and Q 54 , and NPN transistor Q 55 is matched with NPN current mirror transistor Q 56 and scaled with NPN transistor Q 57 .

The bias amplifier transistors Q 51 and Q 55 operate at the same current level as the current mirror transistors of the two legs of the current generator, and the bias amplifier 50 biases the PNP current mirror transistor pair Q 52 and Q 53 to produce currents that are equal to the current in the bias amplifier's PNP transistor Q 51 , by means of current mirror action with PNP transistor Q 52 .

Adding the bias amplifier circuit results in a positive feedback circuit containing transistors Q 55 -Q 51 for the base drive to the current mirror transistors Q 52 and Q 53 , and serving to clamp the collector voltages of current mirror transistors Q 56 and Q 57 at the same base-emitter voltage (V BE55 =V BE56 ) of transistors Q 55 and Q 56 , respectively. In addition, a negative feedback circuit is formed by transistor Q 57 and resistor R 51 . For stability, the gain of the negative feedback circuit may be made greater than that of the positive feedback circuit, by connecting a capacitor across the base and collector of transistor Q 55 , so as to provide a rapid roll-off in the gain of the positive feedback circuit at high frequencies.

In operation, with the base of the V CE -controlling NPN transistor Q 55 connected to the collector of NPN transistor Q 56 , any current differences between transistors Q 55 and Q 56 are due to base currents required by the PNP transistors Q 51 through Q 54 , and differences in the collector-emitter voltages V CE of the two NPN transistors Q 55 and Q 56 . If the first set of matched PNP transistors Q 51 -Q 54 have reasonably high betas, their base currents will cause only a small percentage of error. Also, the early voltage effects described above with reference to FIG. 4 will cause only small differences in their collector currents.

The NPN transistor Q 55 clamps the collector voltage of NPN transistor Q 56 in the leg containing transistor Q 52 at one base-emitter voltage (V BE55 ) above the supply rail (GND) to which its emitter is connected. With transistors Q 55 and Q 56 being matched, and with the base of the NPN transistor Q 56 connected to the collector of the NPN transistor Q 57 in the leg containing transistor Q 53 , then the NPN transistor Q 56 similarly clamps the collector voltage of NPN transistor Q 57 at one base-emitter voltage (V BE56 ) above the supply rail (GND) to which its emitter is connected. Therefore, the V CE of the current mirror transistor Q 56 will be very close to that of current mirror transistor Q 53 . As a result, the current through the leg containing PNP transistor Q 52 and NPN transistor Q 56 will effectively match the current through the leg containing PNP transistor Q 53 (which is mirrored with transistor Q 52 ) and NPN transistor Q 57 (which is ratioed with transistor Q 56 ). This means that the current I OUT generated at the collector of the output transistor Q 54 will be effectively insensitive to variations in the power supply rail voltages.

SUMMARY OF THE INVENTION

In accordance with the present invention, the ability of the auxiliary bias amplifier-incorporating current generator circuit architecture of FIG. 5 to reduce its sensitivity to variations in power supply voltage is augmented by means of temperature compensation circuitry that is effective to make the current generator insensitive to variations in temperature. As will be described, temperature insensitivity is achieved by generating a current that is the sum or composite of two currents having complementary temperature coefficients.

One current has a positive temperature coefficient, being proportional to KT/q (where K is Boltzman's constant, T is temperature °K. and q is charge), divided by the value of a first resistor connected between the emitter of a second polarity current mirror transistor and a power supply rail. The second current (which has a negative temperature coefficient) flows through a second resistor and is proportional to the V BE of a second polarity current mirror transistor divided by the resistance of a second resistor, connected across the base-emitter junction of the second polarity current mirror transistor.

Since this second current has a negative temperature coefficient, the sum of the two currents at the collector of a current mirror transistor can be set to have a positive, negative, or near zero temperature coefficient, based upon the ratioing of the two currents. The generated output current can be made relatively insensitive to both supply voltage variations and temperature changes, as long as a proper resistor ratio is employed.

To minimize any effect of temperature change, the resistors are preferably made of a material having as low a temperature coefficient as possible. The ability of the augmented generator circuit of the invention to provide an output current that is insensitive to variations in power supply voltage and temperature means that the output current may also be used to generate a stable reference voltage, such as that provided by a bandgap voltage generator.

In accordance with a further aspect of the invention, there is provided a new and improved CMOS current generator architecture, which incorporates an auxiliary CMOS amplifier that is configured and biased to reduce its sensitivity to variations in power supply voltage. Like a augmented bipolar current generator, the CMOS current generator may be augmented by temperature compensation circuitry, so as to provide an output current that is insensitive to both variations in power supply voltage and temperature. As such, the CMOS configured circuit of the invention may also be used to generate a stable reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 , 2 and 3 respectively depict conventional bipolar, CMOS and BiCMOS current mirror transistor circuits for generating a reference output current;

FIG. 4 shows the early voltage effect in the collector current vs. collector-emitter voltage characteristic of a typical bipolar transistor;

FIG. 5 is a circuit diagram of a prior art power supply insensitive bipolar current mirror transistor circuit for generating a reference output current;

FIG. 6 shows a bipolar current generator circuit architecture in accordance with the present invention, incorporating temperature compensation circuitry that makes the output current effectively insensitive to changes in supply voltage and temperature;

FIG. 7 shows a reduced voltage BiCMOS architecture version of the temperature compensated current generator circuit of FIG. 6 ;

FIG. 8 shows a bipolar-configured temperature and power supply rejection-compensated current generator circuit architecture for reducing early voltage effects;

FIG. 9 shows an example of a conventional bandgap reference voltage generator implemented using an N-well CMOS architecture;

FIG. 10 is a circuit diagram of a power supply insensitive CMOS current mirror transistor circuit for generating a reference output current in accordance with a further aspect of the present invention;

FIG. 11 shows a modification of the CMOS-implemented bandgap reference voltage generator of FIG. 9 that incorporates the CMOS bias amplifier circuitry of FIG. 10 ;

FIG. 12 shows a further conventional CMOS reference current generator;

FIG. 13 shows a modification of the circuit of FIG. 12 that incorporates CMOS bias amplifier circuitry;

FIG. 14 shows an embodiment of a temperature compensated bipolar transistor-configured bandgap voltage generator;

FIG. 15 is an equivalent CMOS-implemented version of the bandgap voltage generator of FIG. 14 ; and

FIG. 16 shows a complementary current flow polarity equivalent of the CMOS current generator of FIG. 11 .

DETAILED DESCRIPTION

FIG. 6 shows a modification of the bipolar current generator circuit architecture of FIG. 5 in accordance with the present invention, to incorporate temperature compensation circuitry that is effective to make its output current I OUT insensitive to changes in both supply voltage and temperature. In the augmented current generator of FIG. 6 , power supply voltage insensitivity is accomplished in the same manner as the bipolar current generator of FIG. 5 . Temperature insensitivity is realized by generating a composite current that is the sum or composite of two currents having complementary temperature coefficients, such that the resultant current is substantially invariant with temperature.

In the circuit of FIG. 6 , the first of these two complementary currents is a collector current I CQ811 of transistor Q 811 , which has a positive temperature coefficient, increasing as temperature increases. This current is proportional to KT/q (where K is Boltzman's constant, T is temperature (k°) and q is charge), divided by the value of a resistor R 83 connected between the emitter of NPN transistor Q 811 and the ground supply rail. The second current I R82 (which has a negative temperature coefficient) flows through a resistor R 82 and is proportional to the V BE of an NPN transistor Q 810 , divided by the resistance of the resistor R 82 , which is connected across the base-emitter junction of transistor Q 810 . Since the current I R82 through resistor R 82 decreases with increase in temperature, then, depending upon the ratio of the first and second currents, the composite of these currents corresponding to their sum at the collector of current mirror transistor Q 84 can be set to have a positive, negative, or near zero (flat) temperature coefficient.

In the temperature-compensated reference current generator embodiment of FIG. 6 , PNP transistors Q 83 and Q 84 form a primary current mirror. If NPN transistors Q 810 and Q 811 have reasonably high betas, then their base currents are very small compared to their collector currents, so that essentially all of the collector current through the current mirror transistor Q 84 flows into a circuit having a first leg through the collector-emitter path of the transistor Q 811 and the resistor R 83 and a second leg through resistor R 82 . In a similar manner, essentially all of the collector current of current mirror transistor Q 83 will flow into a circuit having a first leg through the collector-emitter path of transistor Q 810 and a second leg through a resistor R 81 .

Similar to the coupling of resistor 82 across the base-emitter junction of transistor Q 810 , resistor 81 is coupled across the base-emitter junction of an NPN transistor Q 86 (which is matched with transistor Q 810 . The collector current path of NPN transistor Q 86 is coupled to a PNP transistor Q 81 , that is connected in current mirror configuration with matched current mirror transistors Q 82 , Q 83 , Q 84 and Q 85 . Similar to a current-diverting or ‘siphoning’ effect of resistor 82 relative to the collector current of current mirror transistor Q 84 , the resistor 81 serves to ‘siphon off’ part of the collector current of the current mirror transistor Q 83 .

Therefore, if the resistors R 81 and R 82 are matched components, and if the voltages across these resistors are also matched, then the currents through resistors R 81 and R 82 will be the same. This means that the collector currents of the transistors Q 810 and Q 811 must match.

As shown in the circuit diagram of FIG. 6 , the geometry (emitter area) of transistor Q 811 is N times that of the transistor Q 810 . By making the ratio N only slightly greater than 1.0 (e.g., 1 . 01 ), a number of benefits can be achieved. For purposes of illustration, transistor Q 810 may be formed of a relatively large first number of identical transistors (e.g., 100 transistors) connected in parallel with each other, and transistor Q 811 may comprise a similarly large second number of identical transistors (e.g., 101 transistors) connected in parallel with each other (so as to result in a geometry ratio that is relatively close to 1, here N:1=101:100).

In such a circuit configuration, although each of transistors Q 810 and Q 811 is formed of a large number of devices in order to obtain a substantial overall emitter area, the geometry difference between the two devices is relatively small. This serves to provide a number of useful effects. First, it effectively integrates out the dispersion of a typical random distribution of defects formed in the two devices during the manufacturing process. Secondly, it serves to balance out their inherent base resistances. Thirdly, and of particular benefit, is the fact that it enables a very small current to be realized by a relatively small valued emitter resistor R 83 , thereby improving integration density, and reducing IR losses.

The collector currents of the transistors Q 810 and Q 811 may be defined in equation (9) as:

I Q810 =I Q811 =V T *ln( N )/ R 83   (9)

As described above, the voltage across the resistor R 82 is established by the V BE of transistor Q 810 , so that the current I R82 through resistor R 82 may be defined in equation (10) as:

I R82 =V BE(Q810) /R 82   (10)

The collector-emitter current ICE(Q 84 ) of transistor Q 84 equals the collector current of transistor Q 811 plus the current through the resistor R 82 . Namely, as shown in equation (11):

I CE(Q84) =V T *ln( N )/ R 83 + V BE(Q 810) /R 82   (11)

By properly setting the ratio of the resistor R 83 to the resistor R 82 , the current I CE(Q84) may be made to have a near zero or substantially ‘flat’ temperature coefficient.

This collector-emitter current I CE(Q84) of PNP transistor Q 84 is mirrored in the matched PNP transistors Q 81 , Q 82 , Q 83 and Q 85 , as shown in equation (12) as:

I CE(Q84) =I Q81 =I Q82 =I Q83 =V T *In ( N )/ R 83 +V BEQ810 /R 82 = I Q85   (12)

An NPN transistor Q 89 is connected in current mirror configuration with NPN transistor Q 810 , with its collector connected to the collector of current mirror transistor Q 82 and to the collector and base of diode-connected NPN transistor Q 88 . The geometry of NPN transistor Q 89 is matched to that of transistor Q 810 , so that the current I Q89 flowing through transistor Q 89 is the same as that flowing through transistor Q 810 and may be defined in equation (13) as:

I Q89 =I Q810 =V T *ln( N )/ R 83   (13)

Subtracting the current I Q89 from the current I Q82 causes the current to flowing through the diode-connected NPN transistor Q 88 (the collector-emitter path of which is coupled in parallel with NPN transistor Q 89 ) to be proportional to the V BE of NPN transistor Q 810 , as set forth in equation (14).

I Q88 =I Q82−I Q89 =V T *ln ( N )/ R 83 +V BE(Q810) /R 82 − V T *ln( N )/ R 83   (14)

The current I Q88 is mirrored by an NPN transistor Q 87 , the base of which is coupled to the base of NPN transistor Q 88 and the collector-emitter path of which is coupled in parallel with that of an NPN transistor Q 86 to the collector of current mirror transistor Q 81 . As can be seen from this circuit connection, and as is shown in equations (15) and (16), the current I Q87 mirrored in NPN transistor Q 87 is therefore subtracted from the current of the PNP transistor Q 81 , resulting in the current flowing through the transistor Q 86 being proportional to V T . Namely:

I Q87 =I Q88 =V BE(Q810) /R 82   (15)

I Q86 =I Q81 =I Q87 =V T *ln ( N )/ R 83 + V BE(Q810) /R 82 = V T *ln( N )/ R 83   (16)

It can be seen therefore, that the circuit containing transistors Q 82 , Q 87 and Q 89 serves as a second order refinement to the first order balancing effect of transistors Q 81 and Q 86 to transistor Q 810 . As a consequence, since the NPN transistors Q 86 and Q 810 are matched transistors, and they both have approximately the same currents flowing through them, their base-emitter voltages V BE86 and V BE810 will be nearly identical. These V BE voltages are applied across the resistor R 81 , which is coupled across the base-emitter junction of NPN transistor Q 86 , and resistor R 82 , which is coupled across the base-emitter junction of NPN transistor Q 810 , and generate the nearly equal currents referenced above.

It will be appreciated therefore that the generated current I OUT will be relatively insensitive to both supply voltage variations and temperature variations, as long as the correct ratio of resistor R 83 to the matched resistor pair R 81 and R 82 is used. Preferably, resistors R 81 , R 82 and R 83 are made of a material having as low a temperature coefficient as possible, to minimize temperature variations. The circuit architecture of FIG. 6 can function with a power supply voltage as low as 2*V BE . Therefore, a 2V power supply can be employed even at very low temperatures.

A reduced voltage version of the generator circuit of FIG. 6 may be implemented using a BiCMOS architecture as shown in FIG. 7 . The generator circuit of FIG. 7 functions in the same way as the circuit in FIG. 6 , except that the PNP bipolar transistors Q 81 -Q 85 of FIG. 6 have been replaced by PMOS devices P 91 -P 95 . These PMOS devices will continue to operate in their saturated regions, as long as V DS >(V GS−V T ). Therefore, these devices can operate at very low V DS voltages. Indeed, the BiCMOS circuit shown in FIG. 7 can operate with a power supply voltage lower than one volt.

A shortcoming of the circuit of FIG. 6 is the current mirror formed by transistors Q 87 and Q 88 . The collector-emitter voltage V CE of transistor Q 88 is equal to the base-emitter voltage V BE of current mirror transistor Q 88 , while the collector-emitter voltage V CE of transistor Q 87 is equal to the supply rail voltage Vcc minus the base-emitter voltage V BE of transistor Q 81 . Early voltage effects will cause a current mismatch between transistors Q 88 and Q 87 , which has a small effect on the PSR of the output current I OUT .

A current generator circuit architecture for reducing this problem is shown in FIG. 8 . That portion of the circuit of FIG. 8 that generates a current proportional to V T consists of a current mirror circuit comprised of PNP current mirror transistors Q 106 , Q 107 , and NPN ratioed transistors Q 1010 , Q 1011 , and a resistor R 102 , which is coupled in the collector-emitter current path of transistor Q 1011 . PNP current mirror transistors Q 106 and Q 107 have matched emitter areas. Ratioed NPN transistor Q 1011 has N times the emitter area of NPN transistor Q 1010 . With the currents through transistors Q 1010 and Q 1011 matched, due to the current source formed by PNP transistors Q 106 and Q 107 .

The respective collector currents I Q106 and I Q107 of PNP transistors Q 106 and Q 107 are the same and may be defined in equation (17) as:

I Q106 =I Q107 =VT *ln( N )/ R 102   (17)

The collector current I Q103 through PNP transistor Q 103 is defined in equation (18) as:

I Q 103 =I Q106 +I Q107 +I R101 −2 * V T *ln( N )/ R 102 +I R101   (18)

The current through the resistor R 101 is defined by the sum of the V BE of transistor Q 108 and the base-emitter voltage V BE of transistor Q 107 , defined in equation (19) as:

I R 101 =2 V BE /R 101   (19)

The current I Q103 through transistor Q 103 is the sum of a current proportional to VT and a current proportional to V BE , defined in equation (20) as:

I Q103 =2 *V T *ln( N )/ R 102 +2 V BE /R 101   (20)

By the proper choice of resistor ratio of R 101 to R 102 , the temperature coefficient of this current I Q103 can be set close to zero. The power supply rejection of the current proportional to V T depends on how well the collector-emitter voltages V CE of transistors Q 106 and Q 107 match one another, as the power supply voltage is varied.

Since the emitters of transistors Q 106 and Q 107 are connected together, the collector-emitter voltage V CE match of transistors Q 106 and Q 107 depends on their collector voltages. The collector voltage of transistor Q 107 is set by the base-emitter voltage V BE of transistor Q 1010 . The current through transistor Q 1010 is mirrored by transistor Q 109 . Transistor Q 105 has its collector-emitter current path coupled in cascode with transistor Q 109 to keep the collector-emitter V CE voltages of transistors Q 1010 and Q 109 close to each other.

As shown in equation (21), the V CE(Q1010) of transistor NPN Q 1010 equals the V BE(Q108) of NPN transistor Q 108 as:

V CE(Q10101) =V BE(Q108)   (21)

The V CE(Q109) of transistor Q 109 equals the sum of the base-emitter voltage V BE(Q108) of transistor Q 108 , plus the base-emitter voltage V BE(Q107) of transistor Q 107 minus the base-emitter voltage V BE(105) of transistor Q 105 , as set forth in equation (22).

V CE(Q10101) =V BE(Q108) +V BE(Q107) −V BE(Q105)   (22)

Since the base-emitter voltage V BE of an NPN transistor and that of a PNP transistor are substantially equal to each other, the collector-emitter voltages of transistors Q 109 and Q 1010 are substantially the same. In the current mirror formed by PNP transistors Q 101 and Q 102 , the V CEQ102 of diode-connected transistor Q 102 is equal to the V BEQ102 of Q 102 , and the V CEQ101 of transistor Q 101 is equal to the V BEQ103 of transistor Q 103 .

These two V BE voltages will remain approximately equal to each other as the power supply voltage is varied. Therefore, the emitter current of transistor Q 108 will approximately match the emitter current of transistor Q 1010 . If the emitter areas of transistors Q 108 and Q 1010 are matched, their V BE voltages will match.

Matching or equating the respective collector voltages V C(Q106) and V C(Q107) of transistors Q 106 and Q 107 improves the PSR of the current that is proportional to V T . These voltages are defined individually in equations (23) and (24) as:

V C(Q106) =V BE(Q108)   (23)

V C(Q107) =V BE(Q1010)   (24)

The current I R103 through resistor R 101 equals the sum of the V BEQ107 of transistor Q 107 plus the V BEQ108 of transistor Q 108 divided by the resistance of resistor R 101 . Both of these V BE voltages are relatively insensitive to power supply variations, because they are determined by currents proportional to V T . Therefore, the current through resistor R 101 will also be relatively insensitive to supply voltage variations. The currents proportional to V T and V BE are provided by transistor Q 103 and are mirrored as I OUT by transistor Q 104 . With the proper ratio of resistors R 101 to R 102 , the generated output current I OUT will have a high PSR and a low temperature variation.

As pointed out briefly above, because the dual compensated current generator circuit of the invention is operative to provide an output current that is effectively insensitive to variations in both power supply voltage and temperature, this output current may be used to generate a stable reference voltage, such as that provided by a bandgap voltage generator.

An example of a conventional bandgap reference voltage generator implemented using an N-well CMOS architecture is diagrammatically illustrated in FIG. 9 . The conventional circuit of FIG. 9 effectively corresponds to the circuit diagram shown on page 597 of the text by P. Allen et al, entitled: “CMOS Analog Circuit Design,”, published by Harcourt Brace Jovanovich College Publishers, 1987. The bandgap reference voltage circuit of FIG. 9 generates a (bandgap) reference voltage V OUT , that is ideally equal to:

V OUT =V BE(Q113) +R 112 * V T *ln( N )/ R 111   (25)

For the proper ratio of resistors R 111 and R 112 , V OUT will be relatively constant over a reasonably large temperature range. However, variations in the power supply voltage will have a noticeable affect on V OUT due to the channel length modulation of MOSFETs P 111 and P 112 .

FIG. 10 shows a modification of the circuit of FIG. 9 , that incorporates CMOS-configured bias amplifier circuitry in accordance with a further aspect of the present invention, shown in FIG. 11 , so that the power supply rejection of the voltage generator of FIG. 10 can be increased without any additional operating headroom. A NWELL process equivalent of the PWELL process CMOS circuit of FIG. 11 is shown in FIG. 16 . In order to avoid unnecessarily encumbering the present description with details that are readily apparent to one skilled in the art, the architecture of FIG. 11 will be explained. From this explanation, application of the CMOS circuit of FIG. 11 to realize the complementary circuit embodiment of FIG. 16 is straightforward.

In the CMOS-configured power supply variation compensated current generator of FIG. 11 , the voltages across associated MOSFETs of the two current mirror legs containing CMOS MOSFET pairs P 62 -N 62 and P 63 -N 63 , and associated bipolar transistors Q 62 and Q 63 and resistor R 63 are effectively equalized by means of an auxiliary CMOS bias amplifier formed of a current mirror N channel MOSFET N 61 , P channel MOSFET P 61 and PNP transistor Q 61 . The bias amplifier MOSFETs have their source-drain current paths connected in parallel with those of CMOS pairs of the two current mirror legs that are connected between the power supply rails (Vcc and ground).

P channel MOSFET P 61 of the auxiliary CMOS bias amplifier is connected in a diode configuration, having its drain connected to its gate, with the gate of P channel MOSFET P 61 connected in common to the gates of P channel MOSFETs P 62 , P 63 and P 64 , with which auxiliary amplifier P-channel MOSFET P 61 forms a current mirror. The gate of the N channel MOSFET N 61 of the auxiliary CMOS bias amplifier is coupled to the drain current path of that leg of the current generator containing P channel current mirror MOSFET P 62 and N channel current mirror MOSFET N 62 . The P channel MOSFET P 61 of the CMOS bias amplifier is matched with P channel current mirror MOSFETs P 62 , P 63 and P 64 , and N channel MOSFET N 61 is matched with N channel current mirror MOSFETs N 62 and N 63 .

The bias amplifier MOSFETs P 61 and N 61 operate at the same current level as the current mirror MOSFETs of the two legs of the current generator, and the bias amplifier biases the P channel current mirror MOSFET pair P 62 and P 63 to produce currents that are equal to the current in the bias amplifier's P channel MOSFET P 61 , by means of current mirror action with P channel MOSFET P 62 . Adding the bias amplifier circuit results in a positive feedback circuit containing MOSFETs P 61 -N 61 for the gate drive to the current mirror P channel MOSFETs P 62 and P 63 , and serving to clamp the drain voltage of current mirror N channel MOSFETs N 62 at approximately the same drain voltage as N channel MOSFETs N 63 . In addition, a negative feedback circuit is formed by N channel MOSFET N 63 and resistor R 63 .

In operation, since the gate of N channel MOSFET N 61 is connected to the drain N channel MOSFET N 62 , current differences between N channel MOSFETs N 61 and N 62 are the result of the gate-source voltages for the P channel MOSFETS P 61 -P 64 , and differences in the drain-source voltages V DS of N channel MOSFETs N 61 and N 62 . The bias amplifier's N channel MOSFET N 61 clamps the drain voltage of N channel MOSFET N 62 at the gate-source voltage V GSN61 , plus the base-emitter voltage V BEQ61 of NPN transistor Q 61 above the supply rail to which its base and collector are connected.

Since N channel MOSFETS N 61 and N 62 are matched, NPN transistors Q 61 and Q 62 are matched, MOSFETs N 61 and N 62 are operating at the same current, the gate of the N channel MOSFET N 61 clamps the drain voltage of N channel MOSFET N 62 at the gate voltage V GN62 , which equals the drain voltage of N channel MOSFET N 63 . N channel MOSFET N 63 is matched to N channel MOSFETs N 61 and N 62 , and bipolar transistor Q 63 is N times the emitter area of transistors Q 61 and Q 62 . The output current I OUT will therefore be given by equation (26) as follows:

I OUT =V T *ln( N )/ R 63   (26)

As a result, the current I OUT generated at the drain of the output P channel MOSFET P 64 is effectively insensitive to variations in the power supply voltages.

In the voltage generator of FIG. 10 , the CMOS current generator circuit of FIG. 11 is modified to incorporate a bipolar transistor Q 124 and a resistor R 122 —enabling the temperature variations of the output current of FIG. 10 to be compensated to generate a stable output voltage V OUT without any additional operating headroom.

In particular, the V BEQ124 of bipolar transistor Q 124 provides a voltage proportional to V BE . The current from transistor P 124 and resistor R 122 provide a voltage proportional to V T . If the resistors R 121 and R 122 are properly selected, the output voltage will be temperature-compensated, as shown in the following equation (27):

V OUT =V BEQ +R 122 * V T *ln( N )/ R 121   (27)

FIG. 12 shows a further conventional CMOS reference current generator, in which matched P channel MOSFETs P 151 and P 152 are connected in a current mirror configuration and N channel MOSFETs N 151 and N 152 have matched gate lengths L P151 and L P152 , but different gate widths W P151 and W P152 .

Namely, L P151 =L P152   (28)

W P151 =W P152 , and  (29)

L P151 =L N152 =L   (30)

Where the gate width W N152 of N channel MOSFET N 152 that is N times the gate width W N151 of N channel MOSFET N 151 . Namely,

N*W N152 =W N152   (31)

Solving equation (31) for the ratio of W N152 to W W151 produces equation (32) as:

N=W N152 /W W151   (32)

If the current mirror formed by P channel MOSFETs P 151 and P 152 is perfectly matched, then the drain-source current I DSP151 of P channel MOSFET P 151 is equal to the I DSP152 of P channel MOSFET P 152 . In addition, the I DSP151 of P channel MOSFET P 151 must equal the I DSN151 of N channel MOSFET N 151 , since MOSFETs P 151 and N 151 are connected in series. Likewise, the I DSP152 of P channel MOSFET P 152 must equal the I DSN112 of N channel MOSFET N 152 , which must also equal the current I R151 through resistor R 151 , which is summarized in equation (38). For simplicity this current is referred to as I.

I DSP151 =I DSP152 =I DSN151 =I DSN152 =I R151 =I   (33)

Where N channel MOSFET N 161 is operating in the saturated region, the current I can be calculated using equation (31) as follows: $$ I = K PN * W L * ( V G - V TN ) 2 ⁢   ⁢ where: ⁢   ⁢ K PN = μ N * C OX 2 ( 34 )

Solving equation (34) for V G −V TN yields equation (35) as: $$ V G - V TN = I * L K PN * W N151 ( 35 )

Equation (34) can also be applied to N channel MOSFET N 152 , yielding equation (36) as follows: $$ I = K PN * W N152 L * ( V G - V TN - I * R151 ) 2 ( 36 )

The expression of V G −V T in equation (35) can be substituted in equation (36), yielding equation (37) as follows: $$ I = K PN * W N2 L * ( I * L K PN * W N151 - ( I * R151 ) ) 2 ( 37 )

Solving equation (37) for I and substituting into equation (36) yields equation (38) as: $$ I = L W N151 * K PN * R151 2 * ( 1 - 1 N ) 2 ( 38 )

Equation (38) indicates that the current I is set by K PN , the MOSFET widths W, the MOSFET lengths L, and the value of resistor R 151 . Ideally, this current is independent of the supply voltage. However, mismatches in the drain-source voltages of P channel MOSFETs P 151 and P 152 can cause mismatches in the currents generated by the current mirror. The mismatch in the drain-source voltages of P channel MOSFETs P 151 and P 152 will vary as the supply voltage is varied. Therefore, the output current will also exhibit variation with supply voltage.

In accordance with the invention, this variation can be reduced by incorporating the CMOS bias amplifier described above into the circuit of FIG. 12 , to result in the improved circuit architecture of FIG. 13 . The bias amplifier modification is shown at 160 , and comprises an auxiliary diode-connected P channel MOSFET P 161 that is matched with P channel MOSFETs p 162 -p 164 , and N channel MOSFET N 161 , that is matched with current mirror N channel MOSFETs N 162 and 163 , as shown. As in the circuit of FIG. 7 , the current generator circuit of FIG. 13 can function at very low power supply voltages and is still able to maintain good power supply rejection.

FIG. 14 shows an embodiment of a temperature compensated bipolar transistor-configured bandgap voltage generator circuit using the bias amplifier circuitry of FIG. 5 , and is configured to generate an output reference voltage V OUT that is relatively insensitive to changes in both supply voltage and temperature. An equivalent CMOS-implemented version of the bandgap generator circuit of FIG. 14 that will be readily appreciated from the circuit architecture of FIG. 14 is shown in FIG. 15 .

The dual compensation effect (for power supply and temperature variations) is achieved by forming two independent current generator circuits, shown in FIG. 14 by broken lines 171 and 172 , each of which uses the bias amplifier described above to improve its PSR. The output currents I 171 and I 172 of these two current generator circuits is summed and passed through an output resistor R 174 to produce the reference voltage V OUT .

The current generator circuit 171 is configured to produce output current I 171 in proportion to the thermal voltage V T divided by the difference between the values of resistors R 173 and R 172 , as set forth in equation (39). $$ I171 = V T * ln ⁡ ( N ) ( R173 - R172 ) ( 39 )

The current generator circuit 172 is configured to produce output current I 172 in proportion to the base emitter junction voltage Vbe of transistor Q 175 divided by the difference between the values of resistors R 176 and R 175 , as set forth in equation (40). $$ I172 = V be ⁡ ( Q175 ) ( R176 - R175 ) ( 40 )

By proper choice of the values of these resistors, the output voltage V OUT across resistor R 174 can be made to have a low temperature coefficient. If the resistors are fabricated using a material that is readily laser trimable, such as NiCr, the circuit of FIG. 14 allows I 171 , I 172 , and V OUT to be adjusted during circuit probe operation. The output current I 171 produced by current generator 171 can be increased by increasing the value of resistor R 172 via laser trimming techniques. For a non-limiting example of a mechanism for trimming bias currents either up or down, attention may be directed to U.S. Pat. No. 5,686,822. Conversely, the output current I 171 can be decreased by laser trimming resistor R 173 to increase its value. Similarly, the output current I 172 produced by current generator 172 can be increased or decreased by trimming either resistor R 175 or resistor R 176 . V OUT can be increased by trimming output resistor R 174 .

As will be appreciated from the foregoing description, the present invention augments the reduced sensitivity of an auxiliary bias amplifier-incorporating current generator circuit architecture to variations in power supply voltage by means of temperature compensation circuitry that is effective to make the current generator insensitive to variations in both power supply voltage and temperature. The invention also provides a CMOS current generator architecture having an auxiliary CMOS amplifier that is configured and biased to reduce its sensitivity to variations in power supply voltage. The CMOS current generator may also include temperature compensation circuitry, so as to provide an output current that is insensitive to both variations in power supply voltage and temperature. As such, the CMOS configured circuit of the invention may also be used to generate a stable reference voltage.

While we have shown and described various embodiments in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as are known to a person skilled in the art, and we therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

Claims

1. A current generator comprising:a current mirror circuit coupled between first and second voltage supply terminals, and including an output current mirror transistor from which an output current is derived; an electrical parameter control circuit coupled to said current mirror circuit and being operative to equalize electrical parameters in respective legs of said current mirror circuit independent of a variation in supply voltage coupled to said first and second voltage supply terminals; and a temperature compensation circuit coupled to said current mirror circuit, and containing first and second current flow paths producing respective first and second currents having complementary temperature coefficients and being combined to produce said output current that is effectively insensitive to changes in temperature.

2. The current generator according to claim 1, wherein said first current flow path of said temperature compensation circuit includes a first transistor producing said first current that has a positive temperature coefficient, proportional to KT/q (where K is Boltzman's constant, T is temperature (°C.) and q is charge), and wherein said second current flow path of said temperature compensation circuit produces said second current that has a negative temperature coefficient associated with a PN junction of a second transistor, and wherein said first and second currents are summed into a composite current that is mirrored by said output current mirror transistor to produce said output current.

3. The current generator according to claim 2, wherein said first transistor is coupled in a first leg of said current mirror circuit, and said second current flow path includes a first resistor coupled to a control electrode of said second transistor of said second current flow path, and said first current flow path includes a second resistor coupled in circuit with an output current path electrode of said first transistor.

4. The current generator according to claim 3, further including a first auxiliary transistor coupled in current mirror configuration with said current mirror circuit, a second auxiliary transistor coupled in circuit with said first auxiliary transistor and a third resistor coupled in circuit with said second auxiliary transistor in the same manner as said first resistor is coupled with said second transistor, and being operative to divert current from said second leg of said current mirror circuit.

5. The current generator according to claim 4, wherein said first transistor of said second leg of said current mirror circuit has a geometry larger than that of said second transistor.

6. The current generator according to claim 5, wherein said first transistor is comprised of a first plurality of parallel connected transistor devices and said second transistor is comprised of a second plurality of parallel connected transistor devices, such that the difference between said first and second numbers of transistor devices is at least an order of magnitude less than the numbers of said first and second pluralities of transistor devices.

7. The current generator according to claim 5, wherein said first transistor is comprised of a first plurality of parallel connected transistor devices and said second transistor is comprised of a second plurality of parallel connected transistor devices, such that the difference between said first and second numbers of transistor devices is on the order of two orders of magnitude less than the numbers of said first and second pluralities of transistor devices.

8. The current generator according to claim 4, wherein said first auxiliary transistor is effectively matched with transistors of said current mirror circuit, and wherein said second auxiliary transistor is effectively matched with said second transistor of said second leg of said current mirror circuit.

9. The current generator according to claim 4, further including a third auxiliary transistor coupled in current mirror configuration with said current mirror circuit, a fourth auxiliary transistor coupled in circuit with said third auxiliary transistor and said second transistor of said second leg of said current mirror circuit.

10. The current generator according to claim 9, further including a fifth auxiliary transistor coupled in circuit with said first auxiliary transistor and a sixth auxiliary transistor coupled in circuit with said fifth auxiliary transistor and said third auxiliary transistor.

11. The current generator according to claim 1, wherein said current mirror circuit is configured as a CMOS transistor current mirror circuit.

12. The current generator according to claim 1, further including an output resistor coupled in circuit with said output current mirror transistor and being operative to generate an output voltage in proportion to said output current.

13. A temperature compensated current mirror circuit comprising:a current mirror circuit coupled between first and second voltage supply terminals, and including an output current mirror transistor from which an output current is derived; and a temperature compensation circuit including first and second current flow paths producing respective first and second currents having complementary temperature coefficients and being operative to cause said output current to be effectively insensitive to changes in temperature, said first current flow path including a first transistor producing said first current having a positive temperature coefficient, proportional to KT/q (where K is Boltzman's constant, T is temperature (°C.) and q is charge), said second current flow path producing said second current having a negative temperature coefficient associated with a PN junction of a second transistor, and said first and second currents being summed into a composite current that is mirrored by said output current mirror transistor to produce said output current, and wherein said first transistor is comprised of a first plurality of parallel connected transistor devices and said second transistor is comprised of a second plurality of parallel connected transistor devices, such that the difference between said first and second numbers of transistor devices is at least an order of magnitude less than the numbers of said first and second pluralities of transistor devices.

14. The temperature compensated current mirror circuit according to claim 13, wherein said first transistor is coupled in a first leg of said current mirror circuit, and said second current flow path includes a first resistor coupled to a control electrode of said second transistor of said second current flow path, and said first current flow path includes a second resistor coupled in circuit with an output current path electrode of said first transistor.

15. The temperature compensated current mirror circuit according to claim 13, wherein said first transistor is comprised of a first plurality of parallel connected transistor devices and said second transistor is comprised of a second plurality of parallel connected transistor devices, such that the difference between said first and second numbers of transistor devices is on the order of two orders of magnitude less than the numbers of said first and second pluralities of transistor devices.

16. A CMOS electrical reference generator comprising:a CMOS current mirror circuit coupled between first and second voltage supply terminals; an electrical parameter control circuit coupled to said CMOS mirror circuit and being operative to equalize currents flowing through first and second legs of said CMOS current mirror circuit irrespective of a variation in supply voltage coupled to said first and second voltage supply terminals; an output current CMOS transistor coupled in current mirror configuration with said CMOS current mirror circuit and providing said electrical reference as a prescribed output current that is effectively insensitive to said variation in supply voltage; and a temperature compensation circuit coupled to said CMOS current mirror circuit, and containing first and second current flow paths producing respective first and second currents having complementary temperature coefficients, said first and second currents being combined to produce said prescribed output current that is effectively insensitive to changes in temperature.

17. The CMOS electrical reference generator according to claim 16, further including an output resistor coupled to said output current mirror CMOS transistor, and being operative to provide said electrical reference as an output voltage that is proportional to said prescribed output current and effectively insensitive to said variation in supply voltage.

18. A temperature compensated voltage generator comprising:first and second independently operating complementary temperature coefficient-based current generator circuits which are operative to generate first and second output currents which are summed and coupled to an output resistor to produce a reference voltage; said first current generator circuit being configured to produce said first output current proportional to temperature; and said second current generator circuit being configured to produce a second output current inversely proportional to temperature.

19. The temperature compensated voltage generator according to claim 18, wherein said first current generator circuit comprises a first transistor circuit having a positive temperature coefficient, proportional to KT/q (where K is Boltzman's constant, T is temperature (°C.) and q is charge), and containing a first selectively variable resistance, and wherein said second current generator circuit comprises a second transistor circuit having a negative temperature coefficient associated with a PN junction of a second transistor circuit and having a second selectively variable resistance.