REFERENCE VOLTAGE CIRCUIT AND METHOD FOR DESIGNING THE SAME

Abstract

Reference voltage circuits and methods for designing the same are provided. The reference voltage circuit includes: a reference core unit configured to output a reference voltage; a main amplification unit connected to the reference core unit and configured to form feedback to the reference core unit; and a feedforward amplification unit connected to the main amplification unit and configured to form feedforward to the main amplification unit. The reference core unit, the main amplification unit, and the feedforward amplification unit form a third-order negative feedback loop to improve a power supply rejection ratio of the reference voltage.

Description

TECHNICAL FIELD

The present disclosure relates to the technical field of integrated circuits, and in particular to a reference voltage circuit and a method for designing the same.

BACKGROUND

A reference voltage circuit is a key component of high-precision integrated circuits such as A/D (analog to digital) converters. The accuracy of the reference voltage circuit directly affects the accuracy of the A/D converter. In addition to excellent temperature characteristics, the reference voltage circuit may also require high power supply resistance to be able to maintain high accuracy in an environment with large power supply voltage fluctuations.

SUMMARY

Embodiments of the present disclosure provide reference voltage circuits.

According to exemplary embodiments of the present disclosure, a reference voltage circuit includes: a reference core unit configured to output a reference voltage; a main amplification unit connected to the reference core unit and configured to form feedback to the reference core unit; and a feedforward amplification unit connected to the main amplification unit and configured to form feedforward to the main amplification unit. The reference core unit, the main amplification unit, and the feedforward amplification unit form a third-order negative feedback loop to improve the power supply rejection ratio of the reference voltage.

In some embodiments, the reference core unit includes a first nMOSFET (n-type metal-oxide-semiconductor field-effect transistor), a first resistor, a second resistor, a third resistor, a first NPN transistor, a second NPN transistor, a third NPN transistor, and the fourth NPN transistor. A drain of the first nMOSFET is connected to a power supply voltage, a source of the first nMOSFET is sequentially connected to the first resistor, the second resistor, and a collector of the first NPN transistor in series, the collector of the first NPN transistor is connected to a base of the first NPN transistor, an emitter of the first NPN transistor is connected to a collector of the second NPN transistor, the collector of the second NPN transistor is connected to a base of the second NPN transistor, an emitter of the second NPN transistor is connected to ground, the source of the first nMOSFET is connected in sequence to the third resistor and a collector of the third NPN transistor in series, the collector of the third NPN transistor is connected to a base of the third NPN transistor, an emitter of the third NPN transistor is connected to a collector of the fourth NPN transistor, a collector of the fourth NPN transistor is connected to a base of the fourth NPN transistor, an emitter of the fourth NPN transistor is connected to the emitter of the second NPN transistor, wherein the source of the first nMOSFET is configured to output the reference voltage.

In some embodiments, the ratio of an emitter junction area of the second NPN transistor to an emitter junction area of the fourth NPN transistor is n:1, and the ratio of an emitter junction area of the first NPN transistor to an emitter junction area of the third NPN transistor is n:1, where n is an integer greater than or equal to 1.

In some embodiments, the reference core unit further includes a first capacitor. One end of the first capacitor is connected to the source of the first nMOSFET, and the other end of the first capacitor is connected to the ground.

In some embodiments, the reference core unit further includes a fourth resistor, a fifth resistor, and a sixth resistor. The fourth resistor and the fifth resistor are connected in sequence in series between the emitter of the second NPN transistor and the ground. One end of the sixth resistor is connected to the source of the first nMOSFET, and the other end of the sixth resistor is connected to a common terminal between the fourth resistor and the fifth resistor.

In some embodiments, the sixth resistor includes an adjustable resistor.

In some embodiments, the main amplification unit includes a first PNP transistor, a second PNP transistor, a second nMOSFET, a third nMOSFET, a fifth NPN transistor, a sixth NPN transistor, and a first tail current source. An emitter of the first PNP transistor is connected to the power supply voltage, a base of the first PNP transistor is connected to a base of the second PNP transistor, a collector of the first PNP transistor is connected to a drain of the second nMOSFET, a gate of the second nMOSFET is connected to a bias voltage, a source of the second nMOSFET is connected to a collector of the fifth NPN transistor, a base of the fifth NPN transistor is connected to the collector of the third NPN transistor, a emitter of the fifth NPN transistor is connected to the first tail current source in series and then being grounded, an emitter of the second PNP transistor is connected to the power supply voltage, a collector of the second PNP transistor is connected to a gate of the first nMOSFET, the collector of the second PNP transistor is connected to a drain of the third nMOSFET, a gate of the third nMOSFET is connected to the bias voltage, a source of the third nMOSFET is connected to a collector of the sixth NPN transistor, a base of the sixth NPN transistor is connected to a common terminal between the first resistor and the second resistor, and an emitter of the sixth NPN transistor is connected to the emitter of the fifth NPN transistor.

In some embodiments, the feedforward amplification unit includes a first pMOSFET (p-type metal-oxide-semiconductor field-effect transistor), a second pMOSFET, a fourth nMOSFET, a fifth nMOSFET, and a second tail current source. A source of the first pMOSFET is connected to the power supply voltage, a gate of the first pMOSFET is connected to a gate of the second pMOSFET, a gate of the first pMOSFET is connected to a drain of the first pMOSFET, the drain of the first pMOSFET is connected to a drain of the fourth nMOSFET, a gate of the fourth nMOSFET is connected to the drain of the second nMOSFET, a source of the fourth nMOSFET is grounded after connecting to the second tail current in series, a source of the second pMOSFET is connected to the power supply voltage, a drain of the second pMOSFET is connected to a base of the first PNP transistor, the drain of the second pMOSFET is connected to a drain of the fifth nMOSFET, a gate of the fifth nMOSFET is connected to the drain of the third nMOSFET, and a source of the fifth nMOSFET is connected to the source of the fourth nMOSFET.

In some embodiments, the feedforward amplification unit further includes a second capacitor. One end of the second capacitor is connected to the gate of the fourth nMOSFET, and the other end of the second capacitor is connected to the drain of the fifth nMOSFET.

According to exemplary embodiments of the present disclosure, a method for designing a reference voltage circuit includes: on the basis of forming feedback to a reference core unit through a main amplification unit: using a feedforward amplification unit to form a feedforward to the main amplification unit; using the reference core unit, the main amplification unit, and the feedforward amplification unit to form a third-order negative feedback loop; and using the third-order negative feedback loop to improve a power supply rejection ratio of a reference voltage output by the reference core unit.

The reference voltage circuits and its design methods of some exemplary embodiments of the present disclosure may have the following beneficial effects.

On the basis of forming feedback to a reference core unit through a main amplification unit, by using a feedforward amplification unit to form feedforward to the main amplification unit and using the reference core unit, the main amplification unit, and the feedforward amplification unit to form a third-order negative feedback loop, compared with the second-order negative feedback loop formed by the main amplifier unit and the reference core unit, the gain of the third-order negative feedback loop is higher, which effectively improves the power supply rejection ratio of the reference voltage output by the reference core unit in the third-order negative feedback loop.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram of a reference voltage circuit in prior art;

FIG. 2 is a structural block diagram of a reference voltage circuit according to exemplary embodiments of the present disclosure;

FIG. 3 is a circuit diagram of a reference voltage circuit according to exemplary embodiments of the present disclosure; and

FIG. 4 is another circuit diagram of a reference voltage circuit according to exemplary embodiments of the present disclosure.

EXPLANATION OF REFERENCE NUMBERS

C₁—first capacitor, C₂—second capacitor, 11—first current, 12—second current, N₁—first nMOSFET, N₂—second nMOSFET, N₃—third nMOSFET, N₄—fourth nMOSFET, N₅—fifth nMOSFET, P₁—first pMOSFET, P₂—second pMOSFET, Q₁—first NPN transistor, Q₂—second NPN transistor, Q₃—third NPN transistor, Q₄—fourth NPN transistor, Q₅—first PNP transistor, Q₆—second PNP transistor, Q₇—fifth NPN transistor, Q₈—sixth NPN transistor, R₁—first resistor, R₂—second resistor, R₃—third resistor, R₄—fourth resistor, R₅—fifth resistor, R₆—sixth resistor, S₁—first tail current source, S₂—second tail current source, V_dd—power supply voltage, V_REF—reference voltage, GND—ground, A, B, D, E, F, H—nodes.

DESCRIPTION OF EMBODIMENTS

The embodiments of the present disclosure will be described below with reference to specific examples. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the present disclosure.

Referring to FIG. 1 to FIG. 4, it should be noted that the diagrams provided in exemplary embodiments only illustrate the basic concept of the present disclosure in a schematic manner. The drawings only show the components related to the present disclosure and are not drawn according to the number of components, shapes, and scales. In actual implementation, the pattern, quantity, and scale of each component can be arbitrarily changed, and the layout and type of the component may be more complex. The structures, scales, sizes, etc. shown in the drawings attached to this specification are only used to coordinate with the content disclosed in the specification and are for the understanding and reading of those familiar with this technology. They are not used to limit the conditions for the implementation of the present disclosure, so they have no technical limitations. Any structural modifications, changes in scales, or adjustments in size without affecting the effects that the present disclosure can produce and the purposes that can be achieved, should still fall within the scope of the present disclosure covered by the technical content.

As for the reference voltage circuit shown in FIG. 1, it includes a reference core unit 1 and a main amplification unit 2, which is a basic bandgap reference structure. The inventors found through research that the reference voltage V_REF generated by the reference voltage circuit is greatly affected by the fluctuation of the power supply voltage V_dd, and its power supply suppression capability is weak.

In exemplary embodiments, as shown in FIG. 1, the reference core unit 1 includes a first nMOSFET N₁, a first resistor R₁, a second resistor R₂, a third resistor R₃, a first NPN transistor Q₁, a second NPN transistor Q₂, a third NPN transistor Q₃, a fourth NPN transistor Q₄, and a first capacitor C₁. The drain of the first nMOSFET N₁ is connected to the power supply voltage V_dd. The source of the first nMOSFET N₁ is connected sequentially to the first resistor R₁, the second resistor R₂, and the collector of the first NPN transistor Q₁ in series. The collector of the first NPN transistor Q₁ is connected to the base of the first NPN transistor Q₁. The emitter of the first NPN transistor Q₁ is connected to the collector of the second NPN transistor Q₂. The collector of the second NPN transistor Q₂ is connected to the base of the second NPN transistor Q₂. The emitter of the second NPN transistor Q₂ is connected to the ground GND. The source of the first nMOSFET N₁ is connected sequentially to the third resistor R₃ and the collector of the third NPN transistor Q₃ in series. The collector of the third NPN transistor Q₃ is connected to the base of the third NPN transistor Q₃. The emitter of the third NPN transistor Q₃ is connected to the collector of the fourth NPN transistor Q₄. The collector of the fourth NPN transistor Q₄ is connected to the base of the fourth NPN transistor Q₄. The emitter of the fourth NPN transistor Q₄ is connected to the emitter of the second NPN transistor Q₃. The source of the first nMOSFET N₁ outputs the reference voltage V_REF. One end of the first capacitor C₁ is connected to the source of the first nMOSFET N₁, and the other end of the first capacitor C₁ is connected to the ground GND.

In addition, the ratio of the emitter junction area of the second NPN transistor Q₂ to the emitter junction area of the fourth NPN transistor Q₄ is n:1, and the ratio of the emitter junction area of the first NPN transistor Q₁ to the emitter junction area of the third NPN transistor Q₃ is also n:1, where n is an integer greater than or equal to 1.

In exemplary embodiments, as shown in FIG. 1, the main amplification unit 2 includes a first pMOSFET P₁, a second pMOSFET P₂, a second nMOSFET N₂, a third nMOSFET N₃, a fifth NPN transistor Q₇, a six NPN transistors Q₈, and a first tail current source S₁. The source of the first pMOSFET P₁ is connected to the power supply voltage V_dd. The gate of the first pMOSFET P₁ is connected to the gate of the second pMOSFET P₂. The gate of the first pMOSFET P₁ is also connected to the drain of the first pMOSFET P₁. The drain of the first pMOSFET P₁ is connected to the drain of the second nMOSFET N₂. The gate of the second nMOSFET N₂ is connected to a bias voltage V_b. The source of the second nMOSFET N₂ is connected to the collector of the fifth NPN transistor Q₇. The base of the fifth NPN transistor Q₇ is connected to the collector of the third NPN transistor Q₃. The emitter of the fifth NPN transistor Q₇ is connected sequentially to the first tail current source S₁ and the ground GND in series. The source of the second pMOSFET P₂ is connected to the power supply voltage V_dd. The drain of the second pMOSFET P₂ is connected to the gate of the first nMOSFET N₁. The drain of the second pMOSFET P₂ is also connected to the drain of the third nMOSFET N₃. The gate of the third nMOSFET N₃ is connected to the bias voltage V_b. The source of the third nMOSFET N₃ is connected to the collector of the sixth NPN transistor Q₈. The base of the sixth NPN transistor Q₈ is connected to the common terminal between the first resistor R₁ and the second resistor R₂. The emitter of the sixth NPN transistor Q₈ is connected to the emitter of the fifth NPN transistor Q₇.

In more detail, as shown in FIG. 1, under the action of the main amplification unit 2 based on the differential amplifier structure, the voltages of the differential input positive terminal and the differential input negative terminal of the main amplification unit 2 are substancially equal, that is, node A and node B in the reference core unit 1 have the same potential. Therefore, the following equation can be obtained:

$\begin{array}{cc}{V}_{be2}+V_{\mathrm{be}1}+I_1{R}_2=V_{be4}+V_{be3},& \left(1\right)\end{array}$

where V_be1, V_be2, V_be3, and V_be4 are voltage drops of base-emitter junctions of the first NPN transistor Q₁, the second NPN transistor Q₂, the third NPN transistor Q₃, and the fourth NPN transistor Q₄, respectively, and I₁ is the current flowing through the second resistor R₂.

According to the inherent current-voltage relationship of the transistor and the equation (1), the following equation can be obtained:

$\begin{array}{cc}\frac{kT}{q}\ln \frac{I_1}{I_{s2}}+\frac{KT}{q}\ln \frac{I_1}{I_{s1}}+I_1{R}_2=\frac{KT}{q}\ln \frac{I_2}{I_{s4}}+\frac{KT}{q}\ln \frac{I_2}{I_{s3}},& \left(2\right)\end{array}$

where k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, I_s1, I_s2, I_s3, and I_s4 are the reverse saturation currents of the first NPN transistor Q₁, the second NPN transistor Q₂, the third NPN transistor Q₃, and the fourth NPN transistor Q₄, respectively, and I₂ is the current flowing through the third resistor R₃.

By arranging equation (2), the following equation can be obtained:

$\begin{array}{cc}{I}_1=\frac{kT}{q{R}_2}\ln \frac{I_2^2{I}_{s2}{I}_{s1}}{I_1^2{I}_{s4}{I}_{s3}}.& \left(3\right)\end{array}$

According to the operating principle of the transistor, the reverse saturation current of a transistor is proportional to the emitter junction area of the transistor. Given that the ratio of the emitter junction area of the second NPN transistor Q₂ to the emitter junction area of the fourth NPN transistor Q₄ is n:1, and the ratio of the emitter junction area of the first NPN transistor Q₁ to the emitter junction area of the third NPN transistor Q₃ is also n:1, the following equation can be obtained:

$\begin{array}{cc}{I}_1=\frac{2kT}{q{R}_2}\ln \frac{{\mathrm{nI}}_2}{I_1}.& \left(4\right)\end{array}$

Since I₁R₁=I₂R₃, the following equation can be obtained:

$\begin{array}{cc}{I}_1=\frac{2kT}{q{R}_2}\ln \frac{n{R}_1}{R_3}.& \left(5\right)\end{array}$

Since V_REF=V_be2+V_be1+I₁(R₁+R₂), the following equation can be obtained:

$\begin{array}{cc}{V}_{\mathrm{REF}}=2V_{be1}+\frac{2kT\left(R_1+R_2\right)}{q{R}_2}\ln \frac{n{R}_1}{R_3}.& \left(6\right)\end{array}$

Assuming that V_be1 is equal to V_be2, that is, the parameter specifications of the first NPN transistor Q₁ and the second NPN transistor Q₂ are the same, the first term on the right side of equation (6) is a negative temperature coefficient, and the second term is a positive temperature coefficient. The value of the temperature coefficient of the second term on the right side of equation (6) can be modulated by adjusting the specific resistance values of the first resistor R₁, the second resistor R₂, and the third resistor R₃, thereby achieving the compensation and cancellation between the negative temperature coefficient of the first term and the positive temperature coefficient of the second term, so as to obtain a reference voltage V_REF that almost does not change with temperature.

However, as shown in FIG. 1, the potential of node E increases as the power supply voltage V_dd increases, but the electrical level of node F remains approximately unchanged. According to the principle of the main amplification unit 2, the potential of node E increases by ΔV relative to the potential of node F, which will cause the potential of node A to increase by ΔV/G_A1 relative to the potential of node B, where G_A1 is the gain of the main amplification unit 2. The increase in the potential of node A relative to the potential of node B will eventually cause the output reference voltage V_REF to increase by approximately (R₁+R₂)*ΔV/(R₂*G_A1). In the case that the gain G_A1 of the main amplification unit 2 is limited, the reference voltage V_REF generated by the reference voltage circuit shown in FIG. 1 will be very susceptible to fluctuations in the power supply voltage V_dd.

Based on this, the present disclosure proposes a method for designing a reference voltage circuit. For example, on the basis that feedback to a reference core unit is formed by a main amplification unit, a feedforward to the main amplification unit is formed by a feedforward amplification unit, a third-order negative feedback loop is formed by the reference core unit, the main amplification unit, and the feedforward amplification unit, and the power supply rejection ratio of the reference voltage output by the reference core unit is improved through the high gain of the third-order negative feedback loop.

Correspondingly, as shown in FIG. 2, the present disclosure also proposes a reference voltage circuit, which includes: a reference core unit 1 configured to output a reference voltage V_REF; a main amplification unit 2 connected to the reference core unit 1 and configured to form feedback to the reference core unit 1; and a feedforward amplification unit 3 connected to the main amplification unit 2 and configured to form feedforward to the main amplification unit 2, where the reference core unit 1, the main amplification unit 2, and the feedforward amplification unit 3 form a third-order negative feedback loop to improve the power supply rejection ratio of the reference voltage V_REF.

In exemplary embodiments of the present disclosure, as shown in FIG. 3, modification can be made based on the reference voltage circuit shown in FIG. 1. For example, a feedforward amplification unit 3 is added to an output end of the main amplification unit 2 to expand the loop to be a third-order loop.

In exemplary embodiments, as shown in FIG. 3, similar to FIG. 1, the reference core unit 1 includes a first nMOSFET N₁, a first resistor R₁, a second resistor R₂, a third resistor R₃, a first NPN transistor Q₁, a second NPN transistor Q₂, a third NPN transistor Q₃, and a fourth NPN transistor Q₄. The drain of the first nMOSFET N₁ is connected to the power supply voltage V_dd. The source of the first nMOSFET N₁ is connected to the first resistor R₁, the second resistor R₂, and the collector of the first NPN transistor Q₁ in series. The collector of the first NPN transistor Q₁ is connected to the base of the first NPN transistor Q₁. The emitter of the first NPN transistor Q₁ is connected to the collector of the second NPN transistor Q₂. The collector of the second NPN transistor Q₂ is connected to the base of the second NPN transistor Q₂. The emitter of the second NPN transistor Q₂ is connected to the ground GND. The source of the first nMOSFET N₁ is also connected sequentially to the third resistor R₃ and the collector of the third NPN transistor Q₃ in series. The collector of the third NPN transistor Q₃ is connected to the base of the third NPN transistor Q₃. The emitter of the third NPN transistor Q₃ is connected to the collector of the fourth NPN transistor Q₄. The collector of the fourth NPN transistor Q₄ is connected to the base of the fourth NPN transistor Q₄. The emitter of the fourth NPN transistor Q₄ is connected to the emitter of the second NPN transistor Q₃, where the source of the first nMOSFET N₁ outputs the reference voltage V_REF.

In addition, the ratio of the emitter junction area of the second NPN transistor Q₂ to the emitter junction area of the fourth NPN transistor Q₄ is n:1, and the ratio of the emitter junction area of the first NPN transistor Q₁ to the emitter junction area of the third NPN transistor Q₃ is also n:1, where n is an integer greater than or equal to 1.

In exemplary embodiments of the present disclosure, as shown in FIG. 3, the reference core unit 1 also includes a first capacitor C₁, where one end of the first capacitor C₁ is connected to the source of the first nMOSFET N₁, and the other end of the first capacitor C₁ is connected to ground GND. The gain of the third-order negative feedback loop that includes the reference core unit 1, the main amplification unit 2, and the feedforward amplification unit 3 is very large. This third-order negative feedback loop is very easy to oscillate. Therefore, a larger first capacitor C₁ is used to stabilize the entire loop. Generally, the capacitance of the first capacitor C₁ is on the order of microfarads.

In exemplary embodiments, as shown in FIG. 3, similar to FIG. 1, the main amplification unit 2 includes a first PNP transistor Q₅, a second PNP transistor Q₆, a second nMOSFET N₂, a third nMOSFET N₃, a fifth NPN transistor Q₇, a sixth NPN transistor Q₈, and a first tail current source S₁. The emitter of the first PNP transistor Q₅ is connected to the power supply voltage V_dd. The base of the first PNP transistor Q₅ is connected to the base of the second PNP transistor Q₆. The collector of the first PNP transistor Q₅ is connected to the drain of the second nMOSFET N₂. The gate of the second nMOSFET N₂ is connected to the bias voltage V_b. The source of the second nMOSFET N₂ is connected to the collector of the fifth NPN transistor Q₇. The base of the fifth NPN transistor Q₇ is connected to the collector of the third NPN transistor Q₃. The emitter of the fifth NPN transistor Q₇ is connected sequentially to the first tail current source S₁ and ground in series. The emitter of the second PNP transistor Q₆ is connected to the power supply voltage V_dd. The collector of the second PNP transistor Q₆ is connected to the gate of the first nMOSFET N₁. The collector of the second PNP transistor Q₆ is also connected to the drain of the third nMOSFET N₃. The gate of the third nMOSFET N₃ is connected to the bias voltage V_b. The source of the third nMOSFET N₃ is connected to the collector of the sixth NPN transistor Q₈. The base of the sixth NPN transistor Q₈ is connected to the common terminal between the first resistor R₁ and the second resistor R₂. The emitter of the sixth NPN transistor Q₈ is connected to the emitter of the fifth NPN transistor Q₇.

In exemplary embodiments, as shown in FIG. 3, the feedforward amplification unit 3 includes a first pMOSFET P₁, a second pMOSFET P₂, a fourth nMOSFET N₄, a fifth nMOSFET N₅, and a second tail current source S₂. The source of the first pMOSFET P₁ is connected to the power supply voltage V_dd. The gate of the first pMOSFET P₁ is connected to the gate of the second pMOSFET P₂. The gate of the first pMOSFET P₁ is also connected to the drain of the first pMOSFET P₁. The drain of the first pMOSFET P₁ is connected to the drain of the fourth nMOSFET N₄. The gate of the fourth nMOSFET N₄ is connected to the drain of the second nMOSFET N₂. The source of the fourth nMOSFET N₄ is connected sequentially to the second tail current source S₂ and the ground in series. The source of the second pMOSFET P₂ is connected to the power supply voltage V_dd. The drain of the second pMOSFET P₂ is connected to the base of the first PNP transistor Q₅. The drain of the second pMOSFET P₂ is also connected to the drain of the fifth nMOSFET N₅. The gate of the fifth nMOSFET N₅ is connected to the drain of the third nMOSFET N₃. The source of the fifth nMOSFET N₅ is connected to the source of the fourth nMOSFET N₄.

In exemplary embodiments, as shown in FIG. 3, the feedforward amplification unit 3 also includes a second capacitor C₂. For example, one end of the second capacitor C₂ is connected to the gate of the fourth nMOSFET N₄, and the other end of the second capacitor C₂ is connected to the drain of five nMOSFETs N₅.

In exemplary embodiments, for the reference voltage circuit shown in FIG. 3, it is assumed that the potentials of node A and node B are the same at the beginning. If the reference voltage V_REF increases by ΔV, the potential of node A will be higher than the potential of node B by approximately ΔV*R₂/(R₁+R₂). Let G_A1 represent the gain of the main amplifying unit 2. Through the action of the main amplifying unit 2, the potential of node F will be lower than the potential of node E G_A1*ΔV*R₂/(R₁+R₂). G_A2 represents the gain of the feedforward amplifier unit 3. Through the action of the feedforward amplifier unit 3, the potential of node D will increase by G_A2*G_A1*ΔV*R₂/(R₁+R₂). The increase in the potential of node D will cause the potential of node F to decrease by G_D2F*G_A2*G_A1*ΔV*R₂/(R₁+R₂), where G_D2F represents the gain from node D to node F. Therefore, through the action of the main amplification unit 2 and the feedforward amplification unit 3, the potential of the node F decreases by a total of G_A1*ΔV*R₂/(R₁+R₂)+G_D2F*G_A2*G_A1*ΔV*R₂/(R₁+R₂)=(G_A1+G_D2F*G_A2*G_A1)*ΔV*R₂/(R₁+R₂). Through the action of node F to the reference voltage V_REF, the reference voltage V_REF will decrease by (G_A1+G_D2F*G_A2*G_A1)*ΔV*R₂/(R₁+R₂). Therefore, from the reference voltage V_REF to node A, from node A to node F, and from node F back to the reference voltage V_REF, a third-order negative feedback loop is formed. The gain G_loop of the loop is as follows:

$\begin{array}{cc}{G}_{\mathrm{loop}}=\left(G_{A1}+G_{D2F}*G_{A2}*G_{A1}\right)*R_2/\left(R_1+R_2\right)\approx G_{D2F}*G_{A2}*G_{A1}*R_2/\left(R_1+R_2\right),& \left(7\right)\end{array}$

It can be known from the knowledge of integrated circuits that G_D2F, G_A2, and G_A1 are all values of tens or hundreds. Therefore, the gain G_loop of the third-order negative feedback loop can reach a value of tens of thousands. Therefore, a larger loop gain can make the reference voltage V_REF quickly self-correct. When the reference voltage V_REF changes to a high or low level, it can be quickly corrected through the third-order negative feedback loop without fluctuating with the fluctuation of the power supply voltage V_dd. The reference voltage V_REF has an extremely high power supply rejection ratio.

At the same time, such a large loop gain makes the feedback loop (i.e., V_REF→A→F→V_REF) very easy to oscillate, so a larger second capacitor C₂ is used to stabilize the entire loop.

Similar to the analysis in FIG. 1, V_REF in FIG. 3 can be analyzed as follows. Due to the role of the feedback loop (i.e., V_REF→A→F→V_REF), plus its loop gain G_loop is on the order of magnitude of tens of thousands. Therefore, the potentials of node A and node B are approximately equal. Ignoring the influence of the current flowing through the base of the fifth NPN transistor Q₇ and the sixth NPN transistor Q₈, there is:

$\begin{array}{cc}{V}_{be2}+V_{\mathrm{be}1}+I_1{R}_2=V_{be4}+V_{be3},& \left(8\right)\end{array}$

where V_be1, V_be2, V_be3, and V_be4 are voltage drops of the base-emitter junctions of the first NPN transistor Q₁, the second NPN transistor Q₂, the third NPN transistor Q₃, and the fourth NPN transistor Q₄, respectively, and I₁ is the current flowing through the second resistor R₂.

According to the inherent current-voltage relationship of the transistor and equation (1), there is:

$\begin{array}{cc}\frac{kT}{q}\ln \frac{I_1}{I_{s2}}+\frac{KT}{q}\ln \frac{I_1}{I_{s1}}+I_1{R}_2=\frac{KT}{q}\ln \frac{I_2}{I_{s4}}+\frac{KT}{q}\ln \frac{I_2}{I_{s3}},& \left(9\right)\end{array}$

where k is a Boltzmann constant, T is the absolute temperature, q is the electron charge, I_s1, I_s2, I_s3, and I_s4 are reverse saturation current of the first NPN transistor Q₁, the second NPN transistor Q₂, the third NPN transistor Q₃, and the fourth NPN transistor Q₄, respectively. I₂ is the current flowing through the third resistor R₃.

By arranging equation (9), the following equation can be obtained:

$\begin{array}{cc}{I}_1=\frac{kT}{q{R}_2}\ln \frac{I_2^2{I}_{s2}{I}_{s1}}{I_1^2{I}_{s4}{I}_{s3}}.& \left(10\right)\end{array}$

According to the working principle of the transistor, the reverse saturation current of a transistor is proportional to the emitter junction area of the transistor. Since the ratio of the emitter junction area of the second NPN transistor Q₂ to the emitter junction area of the fourth NPN transistor Q₄ is n:1, and the ratio of the emitter junction area of the first NPN transistor Q₁ to the emitter junction area of the third NPN transistor Q₃ is also n:1, the following equation can be obtained:

$\begin{array}{cc}{I}_1=\frac{2kT}{q{R}_2}\ln \frac{{\mathrm{nI}}_2}{I_1}.& \left(11\right)\end{array}$

Since I₁R₁=I₂R₃, the following equation can be obtained:

$\begin{array}{cc}{I}_1=\frac{2kT}{q{R}_2}\ln \frac{n{R}_1}{R_3}.& \left(12\right)\end{array}$

Since V_REF=V_be2+V_be1+I₁(R₁+R₂), the following equation can be obtained:

$\begin{array}{cc}{V}_{\mathrm{REF}}=2V_{be1}+\frac{2kT\left(R_1+R_2\right)}{q{R}_2}\ln \frac{n{R}_1}{R_3}.& \left(13\right)\end{array}$

Like equation (6), the first term on the right side of equation (13) is a negative temperature coefficient, and the second term is a positive temperature coefficient. The value of the temperature coefficient of the second term on the right side of equation (13) can be modulated by adjusting the specific resistance values of the first resistor R₁, the second resistor R₂, and the third resistor R₃, thereby achieving the compensation and cancellation between the negative temperature coefficient of the first term and the positive temperature coefficient of the second term, so as to obtain a reference voltage V_REF that almost does not change with temperature.

At the same time, in FIG. 3, it also forms a feedback loop (i.e., from node E to node D to node E), which will also cause oscillation. Therefore, a second capacitor C₂ (Miller Capacitor) is introduced to stabilize the loop.

In exemplary embodiments, in FIG. 3, if the power supply voltage V_dd increases, the potential of node H will increase. What is different from the circuit of FIG. 1 is that the potential of node D will also increase as the power supply voltage V_dd increases. Therefore, the potential difference between node H and node D is less affected by the power supply voltage V_dd. According to the principle of the feedforward amplification unit 3, compared with the potential difference between node H and node D, the influence of the power supply voltage V_dd on the potential difference between node E and node F is reduced by G_A2 times. According to the principle of the main amplification unit 2, compared with the potential difference between node E and node F, the influence of the power supply voltage V_dd on the potential difference between node A and node B is reduced by G_A1 times. In this way, under the action of the entire third-order negative feedback loop, the reference voltage V_REF is very weakly affected by the power supply voltage V_dd, showing good power supply resistance.

In exemplary embodiments of the present disclosure, as shown in FIG. 4, in order to obtain an accurate reference voltage V_REF (e.g., 2.5V), the reference core unit 1 includes a fourth resistor R₄, a fifth resistor R₅, and the sixth resistor R₆. The fourth resistor R₄ and the fifth resistor R₅ are connected in series between the emitter of the second NPN transistor Q₂ and the ground GND. One end of the sixth resistor R₆ is connected to the source of the first nMOSFET N₁, and the other end of the sixth resistor R₆ is connected to the common end of the fourth resistor R₄ and the fifth resistor R₅. The sixth resistor R₆ includes an adjustable resistor. The sixth resistor R₆ can be adjusted through analog or digital methods. As shown in FIG. 4, by adjusting the resistance of the sixth resistor R₆ through resistor-based voltage division adjustment, an accurate reference voltage V_REF (e.g., 2.5V) can be output.

In summary, in the reference voltage circuit and its design method provided by the present disclosure, on the basis that feedback to a reference core unit is formed by a main amplification unit, by forming feedforward to the main amplification unit using a feedforward amplification unit and forming a third-order negative feedback loop using the reference core unit, the main amplification unit, and the feedforward amplification unit, compared with the second-order negative feedback loop formed by the main amplification unit and the reference core unit, the gain of the third-order negative feedback loop is higher, and the reference voltage can be quickly corrected through the third-order negative feedback loop when changes, such as being too high or too low, or the like, occur to the reference voltage, and will not fluctuate due to fluctuations in the power supply voltage. The reference voltage has an extremely high power supply rejection ratio. In other words, based on the attenuation and buffer against the fluctuations of the power supply voltage due to two larger gains of the main amplification unit and the feedforward amplification unit in the third-order negative feedback loop, the reference voltage is very weakly affected by the fluctuations of the power supply voltage, showing good power supply resistance. At the same time, based on the innovation of the third-order negative feedback loop structure, compared with the current technology, the voltage difference between the two input terminals of the main amplifier unit can remain relatively stable when the power supply voltage changes, thus keeping the reference voltage relatively stable.

The above embodiments only illustrate the principles and effects of the present disclosure and are not intended to limit the present disclosure. Anyone familiar with this technology can modify or change the above embodiments without departing from the scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the present disclosure shall still fall within the scope of the claims of the present disclosure.

Claims

1. A reference voltage circuit, comprising: a reference core unit configured to output a reference voltage;a main amplification unit connected to the reference core unit and configured to form feedback to the reference core unit; anda feedforward amplification unit connected to the main amplification unit and configured to form feedforward to the main amplification unit,wherein the reference core unit, the main amplification unit, and the feedforward amplification unit form a third-order negative feedback loop to improve a power supply rejection ratio of the reference voltage.

2. The reference voltage circuit according to claim 1, wherein the reference core unit includes a first nMOSFET, a first resistor, a second resistor, a third resistor, a first NPN transistor, a second NPN transistor, a third NPN transistor, and a fourth NPN transistor; anda drain of the first nMOSFET is connected to a power supply voltage, a source of the first nMOSFET is sequentially connected to the first resistor, the second resistor, and a collector of the first NPN transistor in series, the collector of the first NPN transistor is connected to a base of the first NPN transistor, an emitter of the first NPN transistor is connected to a collector of the second NPN transistor, the collector of the second NPN transistor is connected to a base of the second NPN transistor, an emitter of the second NPN transistor is connected to ground, the source of the first nMOSFET is connected sequentially to the third resistor and a collector of the third NPN transistor in series, the collector of the third NPN transistor is connected to a base of the third NPN transistor, an emitter of the third NPN transistor is connected to a collector of the fourth NPN transistor, a collector of the fourth NPN transistor is connected to a base of the fourth NPN transistor, an emitter of the fourth NPN transistor is connected to the emitter of the second NPN transistor, wherein the source of the first nMOSFET is configured to output the reference voltage.

3. The reference voltage circuit according to claim 2, wherein a ratio of an emitter junction area of the second NPN transistor to an emitter junction area of the fourth NPN transistor is n:1, and a ratio of an emitter junction area of the first NPN transistor to an emitter junction area of the third NPN transistor is n:1, where n is an integer greater than or equal to 1.

4. The reference voltage circuit according to claim 2, wherein the reference core unit further includes a first capacitor; anda first end of the first capacitor is connected to the source of the first nMOSFET, and a second end of the first capacitor is connected to the ground.

5. The reference voltage circuit according to claim 2, wherein the reference core unit further includes a fourth resistor, a fifth resistor, and a sixth resistor;the fourth resistor and the fifth resistor are connected sequentially in series between the emitter of the second NPN transistor and the ground; anda first end of the sixth resistor is connected to the source of the first nMOSFET, and a second end of the sixth resistor is connected to a common terminal between the fourth resistor and the fifth resistor.

6. The reference voltage circuit according to claim 5, wherein the sixth resistor includes an adjustable resistor.

7. The reference voltage circuit according to claim 2, wherein the main amplification unit includes a first PNP transistor, a second PNP transistor, a second nMOSFET, a third nMOSFET, a fifth NPN transistor, a sixth NPN transistor, and a first tail current source; andan emitter of the first PNP transistor is connected to the power supply voltage, a base of the first PNP transistor is connected to a base of the second PNP transistor, a collector of the first PNP transistor is connected to a drain of the second nMOSFET, a gate of the second nMOSFET is connected to a bias voltage, a source of the second nMOSFET is connected to a collector of the fifth NPN transistor, a base of the fifth NPN transistor is connected to the collector of the third NPN transistor, a emitter of the fifth NPN transistor is grounded after connecting to the first tail current source in series, an emitter of the second PNP transistor is connected to the power supply voltage, a collector of the second PNP transistor is connected to a gate of the first nMOSFET, the collector of the second PNP transistor is connected to a drain of the third nMOSFET, a gate of the third nMOSFET is connected to the bias voltage, a source of the third nMOSFET is connected to a collector of the sixth NPN transistor, a base of the sixth NPN transistor is connected to a common terminal between the first resistor and the second resistor, and an emitter of the sixth NPN transistor is connected to the emitter of the fifth NPN transistor.

8. The reference voltage circuit according to claim 7, wherein the feedforward amplification unit includes a first pMOSFET, a second pMOSFET, a fourth nMOSFET, a fifth nMOSFET, and a second tail current source; anda source of the first pMOSFET is connected to the power supply voltage, a gate of the first pMOSFET is connected to a gate of the second pMOSFET, a gate of the first pMOSFET is connected to a drain of the first pMOSFET, the drain of the first pMOSFET is connected to a drain of the fourth nMOSFET, a gate of the fourth nMOSFET is connected to the drain of the second nMOSFET, a source of the fourth nMOSFET is grounded after connecting to the second tail current source in series, a source of the second pMOSFET is connected to the power supply voltage, a drain of the second pMOSFET is connected to a base of the first PNP transistor, the drain of the second pMOSFET is connected to a drain of the fifth nMOSFET, a gate of the fifth nMOSFET is connected to the drain of the third nMOSFET, and a source of the fifth nMOSFET is connected to the source of the fourth nMOSFET.

9. The reference voltage circuit according to claim 8, wherein the feedforward amplification unit further includes a second capacitor; anda first end of the second capacitor is connected to the gate of the fourth nMOSFET, and a second end of the second capacitor is connected to the drain of the fifth nMOSFET.

10. A method for designing a reference voltage circuit, comprising: on a basis of forming feedback to a reference core unit through a main amplification unit: using a feedforward amplification unit to form a feedforward to the main amplification unit;using the reference core unit, the main amplification unit, and the feedforward amplification unit to form a third-order negative feedback loop; andusing the third-order negative feedback loop to improve a power supply rejection ratio of a reference voltage output by the reference core unit.