Reference voltage circuit

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to a reference voltage circuit that generates a reference voltage of a constant magnitude even when a power supply voltage changes, which is used, for example, as a bias voltage for a constant power supply source of an operational amplifier.

2. Conventional Technology

Conventionally known reference voltage circuits of the type described above include, for example, a reference voltage source described in Japanese Utility Model Patent 62-16682, and a reference voltage circuit described in Japanese Patent 59-41203.

However, the conventional circuits mentioned above are each formed from many MOS transistors, for example, four of them. Such a circuit structure becomes disadvantageously complex. Therefore, it is desired to implement a reference voltage circuit with a simple structure that obtains a desired reference voltage.

Thus, it is a feature of the present invention to provide a reference voltage circuit with a simple structure that can obtain a desired reference voltage regardless of fluctuations in the power supply voltage.

SUMMARY OF THE INVENTION

To solve the problems described above and achieve the feature, the present invention is composed as follows.

Namely, the invention is characterized in that a depletion type first PMOS transistor and an enhancement type second PMOS transistor are serially connected to each other, wherein a gate electrode of the first PMOS transistor is formed from polysilicon including a P-type impurity and connected to a source electrode thereof, a gate electrode of the second PMOS transistor is formed from polysilicon including an N-type impurity and connected to a drain electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the second PMOS transistor and a threshold voltage of the first PMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.

By the structure described above, a voltage corresponding to a difference between a threshold voltage of the second PMOS transistor and a threshold voltage of the first PMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VDD.

Also, the invention is characterized in that an enhancement type first PMOS transistor and a depletion type second PMOS transistor are serially connected to each other, wherein a gate electrode of the first PMOS transistor is formed from polysilicon including an N-type impurity and connected to a drain electrode thereof, a gate electrode of the second PMOS transistor is formed from polysilicon including a P-type impurity and connected to a source electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the first PMOS transistor and a threshold voltage of the second PMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.

By the structure described above, a voltage corresponding to a difference between a threshold voltage of the first PMOS transistor and a threshold voltage of the second PMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VSS.

Furthermore, the invention is characterized in that a depletion type first NMOS transistor and an enhancement type second NMOS transistor are serially connected to each other, wherein a gate electrode of the first NMOS transistor is formed from polysilicon including an N-type impurity and connected to a source electrode thereof, a gate electrode of the second NMOS transistor is formed from polysilicon including a P-type impurity and connected to a drain electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the second NMOS transistor and a threshold voltage of the first NMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.

By the structure described above, a voltage corresponding to a difference between a threshold voltage of the second NMOS transistor and a threshold voltage of the first NMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VDD.

Also, the invention is characterized in that an enhancement type first NMOS transistor and a depletion type second NMOS transistor are serially connected to each other, wherein a gate electrode of the first NMOS transistor is formed from polysilicon including a P-type impurity and connected to a drain electrode thereof, a gate electrode of the second NMOS transistor is formed from polysilicon including an N-type impurity and connected to a source electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the first NMOS transistor and a threshold voltage of the second NMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.

By the structure described above, a voltage corresponding to a difference between a threshold voltage of the first NMOS transistor and a threshold voltage of the second NMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VSS.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

shows a circuit diagram of a structure in accordance with a first embodiment of the present invention.

FIG. 2

shows a cross-sectional view of an example of a physical structure of the first embodiment.

FIG. 3

shows a relation between a power supply voltage and a reference voltage in the first embodiment.

FIG. 4

shows a circuit diagram of a structure in accordance with a second embodiment of the present invention.

FIG. 5

shows a relation between a power supply voltage and a reference voltage in the second embodiment.

FIG. 6

shows a circuit diagram of a structure in accordance with a third embodiment of the present invention.

FIG. 7

shows a cross-sectional view of an example of a physical structure of the third embodiment.

FIG. 8

shows a circuit diagram of a structure in accordance with a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention are described below with reference to the accompanying drawings.

FIG. 1

shows a circuit diagram of a circuit structure of a reference voltage circuit in accordance with a first embodiment of the present invention.

In the reference voltage circuit in accordance with the first embodiment of the present invention, as shown in

FIG. 1

, a depletion type PMOS transistor Q

1

and an enhancement type PMOS transistor Q

2

are serially connected to each other. The serial circuit is connected between a power supply line

1

and a power supply line

2

, and a voltage corresponding to a difference (Vtp

2

−Vtp

1

) between a threshold voltage Vtp

2

of the PMOS transistor Q

2

and a threshold voltage Vtp

1

of the PMOS transistor Q

1

is generated as a reference voltage Vref. The reference voltage Vref is output from an output terminal

3

.

Moreparticularly, the PMOS transistor Q

1

has a gate electrode and a source electrode connected to each other, wherein the mutually connected section is connected to the power supply line

1

. The PMOS transistor Q

1

also has a drain electrode connected to a source electrode of the PMOS transistor Q

2

and the output terminal

3

. The PMOS transistor Q

2

has a gate electrode and a drain electrode connected to each other, wherein the mutually connected section is connected to the power supply line

2

. The source electrode of the PMOS transistor Q

2

is connected to the output terminal

3

. Also, a positive power supply voltage VDD is supplied to the power supply line

1

, and a negative power supply voltage VSS is supplied to the power supply line

2

.

Next, one example of a structure of the PMOS transistors Q

1

and Q

2

is described with reference to FIG.

2

.

The PMOS transistors Q

1

and Q

2

are formed on a P

−

substrate

11

, respectively, as shown in FIG.

2

. More specifically, they are formed in N

−

wells

12

and

13

that are formed in the P

−

substrate

11

.

An N

+

diffusion layer

15

that is connected to a substrate terminal

14

of the PMOS transistor Q

1

, a P

+

diffusion layer

17

that is connected to a source terminal

16

thereof, and a P

+

diffusion layer

19

that is connected to a drain terminal

18

thereof are formed in the N

−

well

12

. A dielectric film

20

composed of silicon oxide is formed at a specified location over the N

−

well

12

, and a gate electrode

21

of the PMOS transistor Q

1

is formed in the dielectric film

20

. The gate electrode

21

is formed from polysilicon including a P-type impurity, and has a P

+

polarity.

An N

+

diffusion layer

25

that is connected to a substrate terminal

24

of the PMOS transistor Q

2

, a P

+

diffusion layer

27

that is connected to a source terminal

26

thereof, and a P

+

diffusion layer

29

that is connected to a drain terminal

28

thereof are formed in the N

−

well

13

. A dielectric film

30

composed of silicon oxide is formed at a specified location over the N

−

well

13

, and a gate electrode

31

of the PMOS transistor Q

2

is formed in the dielectric film

30

. The gate electrode

31

is formed from polysilicon including an N-type impurity, and has an N

+

polarity.

For the PMOS transistors Q

1

and Q

2

having the structure described above, the PMOS transistor Q

1

is a depletion type transistor, and the PMOS transistor Q

2

is an enhancement type transistor. The reason why the PMOS transistor Q

1

is a depletion type transistor is described below.

The threshold voltage Vtp

1

of the PMOS transistor Q

1

can be made lower than the threshold voltage Vtp

2

of the PMOS transistor Q

2

. This is because the polarities of the gate electrodes of the PMOS transistors Q

1

and Q

2

are different. Accordingly, the work functions φ

M

of the gate electrodes are different, whereby the threshold voltages become different. The work function of a gate electrode is greater when the polarity of the gate electrode is P

+

. Also, the work function φ

M

itself can be adjusted by the impurity concentration of the gate electrode.

Therefore, adjusting the impurity concentration of the gate electrodes and the concentration of the wells can change the work functions φ

M

of the gate electrodes and the work function φ

S

of the silicon substrate/, and the PMOS transistor Q

1

can be made into a depletion type transistor. In other words, its threshold voltage Vtp

1

can be made to have a relation Vtp

1

<0.

Next, the reason why the threshold voltage Vtp

1

of the PMOS transistor Q

1

is lower than the threshold voltage Vtp

2

of the PMOS transistor Q

2

is described in detail.

The threshold voltage Vtp of the PMOS transistor is generally determined by Formula (1) shown below.

Vtp=−{2φ

F

+φ

M

−φ

S

−(

Q

B

/C

0

)−(

Q

SS

/C

0

)} (1)

In Formula (1), φ

F

is Fermi level of the silicon substrate, φ

M

is a work function of the gate electrode, φ

S

is a work function of the silicon substrate, Q

B

is a charge amount in the surface of the silicon, Q

SS

is an interfacial charge amount between the silicon and the oxide film, and C

0

is a capacity per unit area of the gate.

In Formula (1), the work function φ

M

of the gate electrode is singly determined by the material of the gate electrode. Also, the work function φ

S

of the silicon substrate may be singly determined if the impurity distribution is uniform.

Therefore, in the case that the gate electrode is formed from polysilicon, a change in the concentration of the impurity to the gate electrode changes the work function φ

M

of the gate electrode. In comparing the work function φ

MP

of a polysilicon gate electrode having a P

+

polarity with the work function φ

MN

of a polysilicon gate electrode having an N

+

polarity, it is noted that the work function of the polysilicon gate electrode having the P

+

polarity is larger.

In other words, the work function φ

MP

and the work function φ

MN

have a relation defined by Formula (2) as follows:

φ

MP

−φ

MP

>0 (2)

As a result, the threshold voltage Vtp

1

of the PMOS transistor Q

1

and the threshold voltage Vtp

2

of the PMOS transistor Q

2

are represented by Formula (3) and Formula (4), respectively, as follows:

Vtp

1

=−{

2

φ

F

+φ

MP

−φ

S

−(

Q

B

/C

0

)−(

a

SS

/C

0

)} (3)

Vtp

2

=−{

2

φ

F

+φ

MN

−φ

S

−(

Q

B

/C

0

)−(

Q

SS

/C

0

)} (4)

Furthermore, the following Formula (5) is established according to Formulas (2) through (4).

Vtp

2

−Vtp

1

=φ

MP

−φ

MN

>0 (5)

It is understood from Formula (5) that the threshold voltage Vtp

1

of the PMOS transistor Q

1

is lower than the threshold voltage Vtp

2

of the PMOS transistor Q

2

.

Next, an operation of the reference voltage circuit in accordance with the first embodiment of the present invention having the structure described above is explained with reference to FIG.

1

.

Since the PMOS transistor Q

1

is a depletion type transistor, current flows even when its gate-source voltage is zero. The PMOS transistor Q

1

normally operates within a range that a power supply voltage VDD is supplied so as to establish a relation of Vgs−Vtp=0−Vtp<Vds, in other words, a relation of Vgs−Vtp<Vds when a gate-source voltage is Vgs, a threshold voltage is Vtp and a drain-source voltage is Vds. The PMOS transistor Q

1

also operates in the saturation region in this instance. Therefore, the drain current I

1

in the PMOS transistor Q

1

is represented by Formula (6) as follows:

I

1

=β/2(0−Vtp

1

)

2

(6)

It is noted that, in Formula (6), β is a parameter to be determined by the process.

Also, the PMOS transistor Q

2

also operates in the saturation region, since its Vgs=Vds, a relation of Vgs−Vtp<Vds is established. Therefore, the drain current I

2

in the PMOS transistor Q

2

is represented by Formula (7) as follows:

I

2

=β/2(

Vref−VSS

−Vtp

2

)

2

(7)

It is noted that, in Formula (7), Vref of the output terminal

3

is a reference voltage, and VSS is a power supply voltage.

When the current that flows in the output terminal

3

is zero, Formula (6) is equal to Formula (7), and the following Formula (8) is obtained.

0−Vtp

1

=

Vref−VSS

−Vtp

2

(8)

Given with Formula (8), a voltage between the output terminal

3

and the power supply voltage VSS, namely, the reference voltage Vref is given by Formula (9) as follows:

Vref=VSS

+(Vtp

2

−Vtp

1

) (9)

In Formula (9), the threshold voltage Vtp

1

and the threshold voltage Vtp

2

has a relation of Vtp

2

>Vtp

1

, such that a constant voltage defined by a difference (Vtp

2

−Vtp

1

) between the threshold voltage Vtp

1

and the threshold voltage Vtp

2

based on the power supply voltage VSS as a reference can be obtained as the reference voltage Vref. Therefore, the reference voltage Vref does not depend on variations in the power supply voltage VDD and becomes constant.

It is noted that the relation among the power supply voltage VDD, the reference voltage Vref and the power supply voltage VSS is shown in FIG.

3

.

Next, a reference voltage circuit in accordance with a second embodiment of the present invention is described with reference to FIG.

4

.

In the reference voltage circuit in accordance with the second embodiment of the present invention, as shown in

FIG. 4

, an enhancement type PMOS transistor Q

3

and a depletion type PMOS transistor Q

4

are serially connected to each other, wherein the serial circuit is connected between a power supply line

1

and a power supply line

2

. A voltage corresponding to a difference (Vtp

3

−Vtp

4

) between a threshold voltage Vtp

3

of the PMOS transistor Q

3

and a threshold voltage Vtp

4

of the PMOS transistor Q

4

is generated as a reference voltage Vref, and the reference voltage Vref is output from an output terminal

3

.

It is noted that the reference voltage circuit in accordance with the second embodiment of the present invention corresponds to the one in which the PMOS transistor Q

1

and the PMOS transistor Q

2

of the first embodiment shown in

FIG. 1

are disposed in mutually reversed locations.

More particularly, the PMOS transistor Q

3

has a source electrode that is connected to the power supply line

1

, and a gate electrode and a drain electrode thereof being connected to one another, wherein the mutually connected section is connected to the output terminal

3

and a source electrode of the PMOS transistor Q

4

. Also, the PMOS transistor Q

4

has a gate electrode and the source electrode connected to each other, wherein the mutually connected section is connected to the output terminal

3

. A drain electrode of the PMOS transistor Q

4

is connected to the power supply line

2

.

The PMOS transistor Q

3

has the same structure as that of the PMOS transistor Q

2

, and its gate electrode is composed of polysilicon including an N-type impurity and has a N

+

polarity. Also, the PMOS transistor Q

4

has the same structure as that of the PMOS transistor Q

1

, and its gate electrode is composed of polysilicon including a P-type impurity and has a P

+

polarity.

Next, an operation of the reference voltage circuit in accordance with the second embodiment of the present invention having the structure described above is explained with reference to FIG.

4

.

Since the PMOS transistors Q

3

and Q

4

operate in the saturation region, the drain currents I

3

and I

4

of the respective PMOS transistors Q

3

and Q

4

are represented by Formulas (10) and (11), respectively, as follows:

I

3

=β/2(

VDD−Vref

−Vtp

3

)

2

(10)

I

4

=β/2(0−Vtp

4

)

2

(11)

Here, in Formula (10), Vref is a reference voltage, VDD is a power supply voltage, and Vtp

3

is a threshold voltage of the PMOS transistor Q

3

. Also, in Formula (11), Vtp

4

is a threshold voltage of the PMOS transistor Q

4

.

When the current that flows out from the output terminal

3

is zero, Formula (10) equals to Formula (11), and the following Formula (12) is obtained.

VDD−Vref

−Vtp

3

=0−Vtp

4

(12)

Based on Formula (12), a voltage between the output terminal

3

and the power supply voltage VDD, namely, the reference voltage Vref is given by Formula (13) as follows:

Vref=VDD

−(Vtp

3

−Vtp

4

) (13)

In Formula (13), the threshold voltage Vtp

3

and the threshold voltage Vtp

4

has a relation of Vtp

3

>Vtp

4

, such that a constant voltage (Vtp

3

−Vtp

4

) defined by a difference between the threshold voltage Vtp

3

and the threshold voltage Vtp

4

based on the power supply voltage VDD as a reference can be obtained as the reference voltage Vref. Therefore, the reference voltage Vref does not depend on variations in the power supply voltage VSS and becomes constant.

It is noted that the relation among the power supply voltage VDD, the reference voltage Vref and the power supply voltage VSS is shown in FIG.

5

.

Next, a reference voltage circuit in accordance with a third embodiment of the present invention is described with reference to FIG.

6

.

In the reference voltage circuit in accordance with the third embodiment of the present invention, as shown in

FIG. 6

, a depletion type NMOS transistor Q

5

and an enhancement type NMOS transistor Q

6

are serially connected to each other. The serial circuit is connected between a power supply line

1

and a power supply line

2

, and a voltage corresponding to a difference (Vtp

6

−Vtp

5

) between a threshold voltage Vtp

6

of the NMOS transistor Q

6

and a threshold voltage Vtp

5

of the NMOS transistor Q

5

is generated as a reference voltage Vref. The reference voltage Vref is output from an output terminal

3

.

More particularly, the NMOS transistor Q

5

has a drain electrode that is connected to the power supply line

1

, and a gate electrode and a source electrode connected to each other, wherein the mutually connected section is connected to a drain terminal of the NMOS transistor Q

6

and the output terminal

3

. The NMOS transistor Q

6

has a gate electrode and a drain electrode connected to each other, wherein the mutually connected section is connected to the output terminal

3

. A source electrode of the NMOS transistor Q

6

is connected to the power supply line

2

.

Next, a structure of the NMOS transistors Q

5

and Q

6

is described with reference to FIG.

7

.

The NMOS transistors Q

5

and Q

6

are formed on an substrate

41

, respectively, as shown in FIG.

7

. More specifically, they are formed in the P

−

wells

42

and

43

that are formed in the N

−

substrate

41

.

An N

+

diffusion layer

45

that is connected to a substrate terminal

44

of the NMOS transistor Q

5

, an N

+

diffusion layer

47

that is connected to a source terminal

46

thereof, and an N

+

diffusion layer

49

that is connected to a drain terminal

48

thereof are formed in the P

−

well

42

. A dielectric film

50

composed of silicon oxide is formed at a specified location over the P

−

well

42

, and a gate electrode

51

of the NMOS transistor Q

5

is formed in the dielectric film

50

. The gate electrode

51

is formed from polysilicon including an N-type impurity.

A P

+

diffusion layer

55

that is connected to a substrate terminal

54

of the NMOS transistor Q

6

, an N

+

diffusion layer

57

that is connected to a source terminal

56

thereof, and an N

+

diffusion layer

59

that is connected to a drain terminal

58

thereof are formed in the P

−

well

43

. A dielectric film

60

composed of silicon oxide is formed at a specified location over the P

−

well

43

, and a gate electrode

61

of the NMOS transistor Q

6

is formed in the dielectric film

60

. The gate electrode

61

is formed from polysilicon including a P-type impurity.

For the NMOS transistors Q

5

and Q

6

having the structure described above, the NMOS transistor Q

5

is a depletion type transistor, and the NMOS transistor Q

6

is an enhancement type transistor. The reason why the NMOS transistor Q

5

is a depletion type transistor is the same as described above for the PMOS transistors Q

1

and Q

2

.

Next, an operation of the reference voltage circuit in accordance with the third embodiment of the present invention having the structure described above is described with reference to FIG.

6

.

Since the NMOS transistor Q

5

is a depletion type transistor, current flows even when its gate-source voltage is zero. Also, the NMOS transistors Q

5

and Q

6

operate in the saturated region. The reasons therefor are the same as those described above with respect to the PMOS transistors Q

1

and Q

2

in the first embodiment. Therefore, the drain current I

5

in the NMOS transistor Q

5

is represented by Formula (14) as follows:

I

5

=β/2(0

−Vtp

5

)

2

(14)

Also, the drain current I

6

in the NMOS transistor Q

6

is represented by Formula (15) as follows:

I

6

=β/2(Vref−VSS−Vtp

6

)

2

(15)

In Formula (15), Vref is a reference voltage, VSS is power supply voltage, and Vtp

6

is a threshold voltage of the NMOS transistor Q

6

.

When the current that flows in the output terminal

3

is zero, Formula (14) is equal to Formula (15), and the following Formula (16) is obtained.

0−Vtp

5

=Vref−VSS

−Vtp

6

(16)

From Formula (16), a voltage between the output terminal

3

and the power supply voltage VSS, namely, the reference voltage Vref is given by Formula (17) as follows:

Vref=VSS

+(Vtp

6

−Vtp

5

) (17)

In Formula (17), the threshold voltage Vtp

6

and the threshold voltage Vtp

5

has a relation of Vtp

6

>Vtp

5

, such that a constant voltage (Vtp

6

−Vtp

5

) defined by a difference between the threshold voltage Vtp

6

and the threshold voltage Vtp

5

based on the power supply voltage VSS as a reference can be obtained as the reference voltage Vref. Therefore, the reference voltage Vref does not depend on variations in the power supply voltage VDD and becomes constant.

Next, a reference voltage circuit in accordance with a fourth embodiment of the present invention is described with reference to FIG.

8

.

In the reference voltage circuit in accordance with the fourth embodiment of the present invention, as shown in

FIG. 8

, an enhancement type NMOS transistor Q

7

and a depletion type NMOS transistor Q

8

are serially connected to each other. The serial circuit is connected between a power supply line

1

and a power supply line

2

, and a voltage corresponding to a difference (Vtp

7

−Vtp

8

) between a threshold voltage Vtp

7

of the NMOS transistor Q

7

and a threshold voltage Vtp

8

of the NMOS transistor Q

8

is generated as a reference voltage Vref. The reference voltage Vref is output from an output terminal

3

.

It is noted that the reference voltage circuit in accordance with the fourth embodiment of the present invention corresponds to the one in which the NMOS transistor Q

5

and the NMOS transistor Q

6

of the third embodiment in

FIG. 6

are disposed in mutually reversed locations.

More particularly, the NMOS transistor Q

7

has a gate electrode and a drain electrode connected to one another, wherein the mutually connected section is connected to the power supply line

1

., The Q

7

also has a source electrode that is connected to the output terminal

3

. Also, the NMOS transistor Q

8

has a gate electrode and a source electrode connected to the power supply line

2

, and a drain electrode connected to the output terminal

3

.

The NMOS transistor Q

7

has the same structure as that of the NMOS transistor Q

6

, and its gate electrode is formed from polysilicon including a P-type impurity and has a P

+

polarity. Also, the NMOS transistor Q

8

has the same structure as that of the NMOS transistor Q

5

, and its gate electrode is formed from polysilicon including an N-type impurity and has an N

+

polarity.

Next, an operation of the reference voltage circuit in accordance with the fourth embodiment of the present invention having the structure described above is described with reference to FIG.

8

.

Since the NMOS transistors Q

7

and Q

8

operate in the saturation region for the reasons similar to those for the NMOS transistors Q

5

and Q

6

, the drain currents I

7

and I

8

of the NMOS transistors Q

7

and Q

8

are given respectively by Formulas (18) and (19), as follows:

I

7

=β/2(

VDD−Vref

−Vtp

7

)

2

(18)

I

8

=β/2(0−Vtp

8

)

2

(19)

Here, in Formula (18), Vref is a reference voltage, VDD is power supply voltage, and Vtp

7

is a threshold voltage of the NMOS transistor Q

7

. Also, in Formula (19), Vtp

8

is a threshold voltage of the NMOS transistor Q

8

.

When the current that flows out from the output terminal

3

is zero, Formula (18) equals to Formula (19) and the following Formula (20) is obtained.

VDD−Vref

−Vtp

7

=0−Vtp

8

(20)

Based on Formula (20), a voltage between the output terminal

3

and the power supply voltage VDD, namely, the reference voltage Vref is given by Formula (21) as follows:

Vref=VDD

−(Vtp

7

−Vtp

8

) (21)

In Formula (21), the threshold voltage Vtp

7

and the threshold voltage Vtp

8

has a relation of Vtp

7

>Vtp

8

, such that a constant voltage (Vtp

7

−Vtp

8

) defined by a difference between the threshold voltage Vtp

7

and the threshold voltage Vtp

8

based on the power supply voltage VDD as a reference can be obtained as the reference voltage Vref. Therefore, the reference voltage Vref does not depend on variations in the power supply voltage VSS and becomes constant.

As described above, with each of the reference voltage circuits in accordance with the first embodiment through the fourth embodiment, a specified reference voltage can be obtained, with a simple structure, but without being affected by influences that are caused by fluctuations in the power supply voltage.

As described above, in accordance with the present invention, a reference voltage circuit that can obtain a specified reference voltage with a simple structure, but without being affected by influences that are caused by fluctuations in the power supply voltage.

The entire disclosure of Japanese Patent Application No. 2000-331251(P) filed Oct. 30, 2000 is incorporated by reference herein.

Number	Name	Date	Kind
4519086	Hull et al.	May 1985	A
4614882	Parker et al.	Sep 1986	A
4760288	Peczalski	Jul 1988	A
4857769	Kotera et al.	Aug 1989	A
4984256	Imai	Jan 1991	A
4996686	Imai et al.	Feb 1991	A
5008565	Taylor	Apr 1991	A
5825695	Hamaguchi	Oct 1998	A

Reference voltage circuit

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