The invention relates to a reference voltage generation circuit, and, more particularly, to a reference voltage generation circuit which is insensitive to element mismatch.
Integrated circuits often require a reference voltage which remains stable under PVT (process, voltage, temperature) variations. A bandgap reference circuit is provided to generate a reference voltage which is not varied with the temperature variation. However, a reference voltage generated by a bandgap reference circuit may vary due to mismatch between elements induced by process variations, such as mismatch between metal-oxide-semiconductor (MOS) transistors of a current mirror circuit within the bandgap reference circuit. Thus, it is desired to provide a bandgap reference circuit which is insensitive to the element mismatch.
An exemplary embodiment of a reference voltage generation circuit for generating an output voltage is provided. The reference voltage generation circuit comprises a bandgap reference circuit and a voltage adjustment circuit. The bandgap reference circuit generates the output voltage at an output node and a reference voltage. The voltage adjustment circuit is coupled to the bandgap reference circuit. The voltage adjustment circuit receives the output voltage and the reference voltage, compares the output voltage with the reference voltage to generate a comparison result, and adjusts the output voltage according to the comparison result.
Anther exemplary embodiment of a reference voltage generation circuit is provided for generating an output voltage at an output node. The reference voltage generation circuit comprises a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, a third resistor, a first operational amplifier, and a voltage adjustment circuit. The first bipolar transistor has a base coupled to a ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a first node. The second bipolar transistor has a base coupled to the ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a second node. The first resistor is coupled between the second node and a third node. The second resistor is coupled to the output node and the first node. The third resistor is coupled to a reference node and the third node. The first operational amplifier has a non-inverting input terminal coupled to the third node, an inverting input terminal coupled to the first node, and an output terminal. The first current mirror circuit is coupled to a voltage source and further coupled to the output node and the reference node. The voltage adjustment circuit is coupled to the output node and the reference node to receive the output voltage and a reference voltage respectively. The voltage adjustment circuit compares the output voltage with the reference voltage to generate a comparison result and adjusts the output voltage according to the comparison result.
Another exemplary embodiment of a reference voltage generation circuit is provided for generating an output voltage at an output node. The reference voltage generation circuit is provided comprises a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, a third resistor, an operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, a current mirror circuit, a first voltage adjustment circuit, and a second voltage adjustment circuit. The first bipolar transistor has a base coupled to a ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a first node. The second bipolar transistor has a base coupled to the ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a second node. The first resistor is coupled between the second node and a third node. The second resistor is coupled to a first reference node and the first node. The third resistor is coupled to a second reference node and the third node. The operational amplifier has a non-inverting input terminal coupled to the third node, an inverting input terminal coupled to the first node, and an output terminal. The fourth resistor is coupled between the third node and the ground terminal. The fifth resistor is coupled between a third reference node and the output node. The sixth resistor is coupled between the output node and the ground terminal. The current mirror circuit is coupled to a voltage source and further coupled to the first, second, and third reference nodes. The first voltage adjustment circuit is coupled to the first reference node and the second reference node to receive a first reference voltage and a second reference voltage respectively. The first voltage adjustment circuit compares the first reference voltage with the second reference voltage to generate a first comparison result and adjusts the first reference voltage according to the first comparison result. The second voltage adjustment circuit is coupled to the second reference node and the third reference node to receive the second reference voltage and a third reference voltage respectively. The second voltage adjustment circuit compares the second reference with the third reference voltage to generate a second comparison result and adjusts the output voltage according to the second comparison result.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Referring to
in
When the reference voltage generation circuit 1 receives a supply voltage VDD through the voltage source VS, the reference voltage generation circuit 1 operates. Based on the operation of the current mirror circuit 21 and the characteristic of the operational amplifier 20, currents I1 and I2 following respectively through the resistors R2 and R3 are generated, and the output voltage Vo and the reference voltage Vref10 are generated at the output node Nout and the reference node Nref10 respectively. Based on the operation of the reference voltage generation circuit 1, the current I2 is represented as:
wherein, V1 represents the voltage at the node N21, V3 represents the voltage at the node N20, ΔVBE represents the difference between the base-emitter voltages of the bipolar transistors Q1 and Q2, and VT represents the threshold voltage of the bipolar transistors. The current I2 is proportional to absolute temperature (i.e. PTAT), that is, the current I2 has a positive temperature coefficient. Since the ratio of width to length of the PMOS transistor M1 is m times the ratio (W/L) of width to length of the PMOS transistor M2, the current I1 is m times the current I2, represented as:
I1=m×I2 Equation (2)
The current I1 is also proportional to absolute temperature. Then, the output voltage Vo is represented as:
wherein, VBE1 represents the base-emitter voltage of the bipolar transistor Q1, which is inversely proportional to absolute temperature (i.e. IPTAT). That is, the base-emitter voltage VBE1 has a negative temperature coefficient. Due to the PTAT current I1 and the IPTAT base-emitter voltage VBE1, the output voltage Vo has a zero temperature coefficient.
In cases (ideal cases) where there is no mismatch between the PMOS transistors M1 and M2 (that is, m=1), Equation (3) is re-written as:
In these ideal cases, the current I1 is equal to the current I2, and, thus, both of the output voltage Vo and the reference voltage Vref10 are equal to a predetermined value, such as 1.25 volts (V). However, in some situations, mismatch may occur between the PMOS transistors M1 and M2 due to process variations, which means that m is larger than or less than 1 (m>1 or m<1). In these cases, the current I1 becomes not equal to the current I2, so that the output voltage Vo is not equal to the reference voltage Vref10, and the output voltage Vo is also not equal to the predetermined value.
According to the embodiment, the voltage adjustment circuit 11 is provided to compensate for the mismatch between the PMOS transistors M1 and M2. Referring to
When the output voltage Vo is less than the reference voltage Vref10 due to the mismatch between the PMOS transistors M1 and M2 (in the cases where m<1), the comparator 22 generates the control signal S22 with a low voltage level to turn on the PMOS transistor Ma, so that, there is a charge path P20 formed between the voltage source VS and the output node Nout. Thus, the output node Nout is charged by the charge path P20 to increase the current I1. Due to the virtual ground of the operational amplifier 20, the voltage V1 at the inverting input terminal is equal to the voltage V2 at the non-inverting input terminal. Based on the equal voltages V1 and V2, the resistors R2 and R3 with the same resistance value, and the operation of the current mirror circuit 21, the current I1 is increased and eventually equal to the current I2, which makes the output voltage Vo equal to the reference voltage Vref10. Thus, the output voltage Vo is eventually adjusted to the predetermined value.
When the output voltage Vo is larger than the reference voltage Vref10 due to the mismatch between the PMOS transistors M1 and M2 (in the cases where m>1), the comparator 22 generates the control signal S22 with a high voltage level to turn on the NMOS transistor Mb, so that, there is a discharge path P21 formed between the output node Nout and the ground terminal GND. Thus, the output node Nout is discharged by the discharge path P21 to decrease the current I1. Based on the equal voltages V1 and V2, the resistors R2 and R3 with the same resistance value, and the operation of the current mirror circuit 21, the current I1 is decreased and eventually equal to the current I2, which makes the output voltage Vo equal to the reference voltage Vref10. Thus, the output voltage Vo is eventually adjusted to the predetermined value.
According to the above embodiment, through the disposition of the resistors R2 and R3 and the operation of the voltage adjustment circuit 11, the output voltage Vo can be adjusted for compensating for the mismatch between the PMOS transistors M1 and M2, such that the reference voltage generation circuit 1 is insensitive to the mismatch induced by the process variations.
According to the structure of the reference voltage generation circuit 1, there is an operational amplifier 20. Usually, the offset voltage of an operational amplifier is in a range 1-10 mV. When the operational amplifier 20 has an offset voltage, the voltage output Vo may have up to 20% error. In order to eliminate the effect of the offset voltage, the reference voltage generation circuit 1 further comprises an offset current generation circuit 12, as shown in
in
Referring to
in
in
In the cases where the offset voltages of the operational amplifier 20 is considered, since m is equal to 1, the current I3 is equal to the current through the resistor R1, and the current I3 is represented as:
Through the operation of the current mirror circuit of the offset current generation circuit 12, the currents I1a, I2a, I3a, and I4a are equal. Thus, when the offset voltages of the operational amplifier 30 is considered, the current I3a is represented as:
Referring to
I1=I3−I3a Equation (7).
Since the resistance value of the resistor R1a is equal to the resistance value of the resistor R1, Equation (7) is re-written, based on Equation (5)˜Equation (7), as:
According to the current I4 and the resistor R2, the output voltage Vo is represented as:
It can be found that Equation (9) is the same as Equation (4), which means that the offset voltage Vos of the operational amplifier 20 is cancelled through the generation of the current I3a (offset current). According to the embodiment of
In the above embodiments, the reference voltage generation circuit 1 generates the output voltage Vo which is larger than 1V, such as 1.25V. In some applications, a stable reference voltage which is less than 1V is required. Thus, according to other embodiments, a reference voltage generation circuit is provided to generate an output voltage which is less than 1V, such as 0.5V. Referring to
Referring to
In the embodiment of
wherein, since V1 has a negative temperature coefficient, the current Ib also has a negative temperature coefficient. In the embodiment, the current I2 is represented as:
I2=I4+Ib Equation (11)
wherein, the current I4 follows through the resistor R1 and has a positive temperature coefficient. Thus, in the embodiment, the current I2 has a zero temperature coefficient. Through the current mirror operation of the PMOS transistors M1 and M3 and the voltage division of the resistors R4 and Ro, the output voltage Vo is generated at the output node Nout.
In ideal cases, there is no mismatch between the PMOS transistors M1 and M2 (that is, m=1) and between the PMOS transistors M2 and M3. However, in some situations, mismatch may occur between the PMOS transistors M1 and M2 (m>1 or m<1), and mismatch may occur between the PMOS transistors M2 and M3, which causes that the output voltage Vo is not equal to a predetermined value, such as 0.5V. As described above, the mismatch between the PMOS transistors M1 and M2 can be compensated for through the operation of the voltage adjustment circuit 11. In the embodiment, the reference voltage generation circuit 1′ further comprises the voltage adjustment circuit 13 to compensate for the mismatch between the PMOS transistors M2 and M3. Referring to
When the reference voltage Vref41 is less than the reference voltage Vref10 due to the mismatch between the MOS transistors M2 and M3, the comparator 40 generates the control signal S40 with a low voltage level to turn on the PMOS transistor Mc, so that, there is a charge path P40 formed between the voltage source VS and the output node Nout. Thus, the reference node Nref41 is charged by the charge path P40 to increase the current Io. Based on the resistors R3 and R4 with the same resistance value and the operation of the current mirror circuit 21′, the current Io is increased and eventually equal to the current I2, which makes the reference voltage Vref41 equal to the reference voltage Vref10. Through the voltage division, the output voltage Vo is eventually equal to the predetermined value with the increment of the current Io.
When the reference voltage Vref41 is larger than the reference voltage Vref10 due to the mismatch between the MOS transistors M2 and M3, the comparator 40 generates the control signal S40 with a high voltage level to turn on the NMOS transistor Md, so that, there is a discharge path P41 formed between the output node Nout and the ground terminal GND. Thus, the reference node Nref41 is discharged by the discharge path P41 to decrease the current Io. Based on the resistors R3 and R4 with the same resistance value and the operation of the current mirror circuit 21′, the current Io is decreased and eventually equal to the current I2, which makes the reference voltage Vref41 equal to the reference voltage Vref10. Through the voltage division, the output voltage Vo is eventually equal to the predetermined value with the decrement of the current Io.
According to the above embodiment, through the disposition of the resistors R2˜R4 and the operations of the voltage adjustment circuit 11 and 13, the output voltage Vo, which is less than 1V, can be adjusted for compensating for the mismatch between the PMOS transistors M1 and M2 and between the PMOS transistors M2 and M3, such that the reference voltage generation circuit 1′ is insensitive to the mismatch induced by the process variations.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Name | Date | Kind |
---|---|---|---|
6507179 | Jun | Jan 2003 | B1 |
10061340 | Rao | Aug 2018 | B1 |
10310528 | Elsayed | Jun 2019 | B1 |
20070146047 | Senriuchi | Jun 2007 | A1 |
20090146730 | Chen | Jun 2009 | A1 |
20100156366 | Sakai | Jun 2010 | A1 |