1. Field of the Invention
The present invention relates to a reference voltage generator for generating a reference voltage within a semiconductor integrated circuit.
2. Description of the Related Art
A circuit used in a reference voltage generator in the related art is described with reference to
First of all, a basic structure of the reference voltage generator is now described with reference to a schematic cross-sectional view of
The D type NMOS transistor 9 which is connected so as to function as a current source includes a buried channel 12 so that the D type NMOS transistor 9 operates with a threshold value in a depletion region. In addition, a drain 17 is used as a power source terminal, and a gate electrode 13 and a source 16 are each connected to a reference voltage generation terminal. By adopting such a connection form, the D type NMOS transistor 9 described above functions as a constant current source. On the other hand, the E type NMOS transistor 10 which is diode-connected to the D type NMOS transistor 9 described above includes a surface channel 11 so that the E type NMOS transistor 10 operates with a threshold value in an enhancement region. In addition, a gate electrode 13 and a drain 15 are each connected to the reference voltage generation terminal, and a source 14 is connected to a ground terminal. That is, the D type NMOS transistor 9 and the E type NMOS transistor 10 are connected in series with each other. Therefore, when the D type NMOS transistor 9 and the E type NMOS transistor 10 are expressed in the form of an equivalent circuit, a circuit diagram illustrated in
Next, an operation of this reference voltage generator is described with reference to
The D type NMOS transistor 9 described above operates as the constant current source. Therefore, for example, a drain current when a gate voltage with a grounded source is applied at regular intervals exhibits D type NMOS transistor characteristics 8 of FIG. 3 as transistor characteristics in this case. In
In the related art, as shown in Japanese Published Patent Application JP56-108258, the reference voltage generator is constructed in such a way that the D type NMOS transistor as the constant current source is operated in the depletion region by the buried channel, and the E type NMOS transistor diode-connected to the D type NMOS transistor is operated in the enhancement region by the surface channel. Here, the drain current characteristics for the gate voltage with the grounded source shown in
In recent years, the improvement of the precision of an electronic apparatus has progressed, and the increased precision of an IC for controlling the electronic apparatus has been required. For example, in the IC, especially, a power management IC represented by a voltage detector or a voltage regulator, along with the miniaturization and the versatility of a portable apparatus to be loaded with the IC, it is required that even when a temperature is changed especially in the inside of the IC due to a change in ambient temperature environment, a reference voltage generator can generate a reference voltage with high precision, that is, temperature characteristics of the reference voltage become flatter.
The present invention has been made in view of the demand described above, and it is therefore an object of the present invention to provide a reference voltage generator having flatter temperature characteristics.
In order to solve the problem described above, a reference voltage generator according to one embodiment of the present invention includes a D type NMOS transistor configured to function as a current source, and a transistor which is diode-connected to the D type NMOS transistor so as to cause a constant current to flow thereinto and which has a circuit configuration of a D type NMOS transistor having the same temperature coefficient as that of the D type NMOS transistor, to thereby have flatter temperature characteristics.
As set forth hereinabove, according to one embodiment of the present invention, the reference voltage generator includes the D type NMOS transistors having the same temperature coefficient, to thereby improve the temperature characteristics of the reference voltage generator.
Now, an embodiment of the present invention is described with reference to the attached drawings.
Firstly, the features of the present invention are described with reference to
In addition, for example, the reference voltage generator includes the two NMOS transistors: the first NMOS transistor having a temperature coefficient D in
Moreover, the reason for this is also because the adjustment of the geometrical sizes of the two NMOS transistors can determine a difference between the threshold values of the two NMOS transistors. For this reason, when the reference voltage generator includes the two NMOS transistors having the same temperature coefficient, the reference voltage as the difference between the threshold voltages can be made approximately constant even if the temperature changes. The threshold voltage A and the threshold voltage B of the respective transistors can be adjusted. For example, the profile of the channel region can be adjusted by using an ion implantation method. Impurities used in this case can be, for example, arsenic for the first NMOS transistor, and phosphorous for the second NMOS transistor.
In addition thereto, with respect to the electrical characteristics of the transistor in this case, as shown in
In the case described above, a schematic circuit diagram of the reference voltage generator is as illustrated in
As a result, the reference voltage generator including the two D type NMOS transistors having the same temperature coefficient as the feature of the present invention can have the flat temperature characteristics.
Number | Date | Country | Kind |
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2013-223367 | Oct 2013 | JP | national |
Number | Name | Date | Kind |
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5467052 | Tsukada | Nov 1995 | A |
5629542 | Sakamoto | May 1997 | A |
6653694 | Osanai | Nov 2003 | B1 |
20080111617 | Krishna | May 2008 | A1 |
20080246064 | Kimura | Oct 2008 | A1 |
Entry |
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Patent Abstracts of Japan, Publication No. 56-108258, Publication Date Aug. 27, 1981. |
Number | Date | Country | |
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20150115930 A1 | Apr 2015 | US |