Dani, Amod K., Ramanan, V. Janaki Govindarajan, R., “Register-Sensitive Software Pipelining”, http://pdps.eece.unm.edu/1998/papers/293.pdf. retrieved using www.google.com, Nov. 6, 2002.* |
Gibbons, Phillip B., Muchnick, Steven S., “Efficient Instruction Scheduling for a Pipelined Architecture”, Hewlett-Packard Laboratories, Palo Alto, CA, 1986 ACM Portal, Nov. 7, 2002.* |
Goodman, James R., Univ of Wisconsin-Madison CS Dept, Hsu, Wei-Chung, Cray Research Inc., “Code Scheduling and Register Allocation in Large Basic Blocks”, 1988 ACM, retrieved from ACM Portal, Nov. 7, 2002.* |
Rau, B. R., Glaeser, C. D., Advanced Processor Technology Group, ESL, Inc., “Some Scheduling Techniques and an Easily Schedulable Architecture for High Performance Scientific Computing”, 1981 IEEE, retrieved from IEEE database, Nov. 7, 2002.* |
Rau, B. Ramakrishna, Glaeser, Christopher D., Picard, Raymond L., Advanced Processor Technology Laboratory, ESL, Inc., “Efficient Code Generation for Horizontal Architectures: Compiler Techniques and Architectural Support”, 1982 IEEE, retrieved Nov. 7, 2002.* |
Shieh, Jong-Jiann and Papachristou, Christos A., Dept of Computer Engineering and Science, Case Western Reserve Univ., “On Reordering Instruction Streams for Pipelined Computers”, 1990 ACM, retrieved from ACM Portal database, Nov. 7, 2002.* |
“Some Experiments in Local Microcode Compaction for Horizontal Machines,” Davidson et al., IEEE Transactions on Computers, vol. C-30, No. 7, Jul. 1981. |
“Local Microcode Compaction Techniques,” Landskov et al., Computing Surveys, vol. 12, No. 3, Sep. 1980. |