Regulated cascode circuits and CMOS analog circuits include the same

Abstract

A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a prior art normal cascode circuit.

FIG. 2 is a circuit diagram illustrating a prior art regulated cascode circuit.

FIG. 3 is a circuit diagram illustrating an example embodiment of a regulated cascode circuit, according to aspects of the present invention.

FIG. 4 is a circuit diagram illustrating another example embodiment of a regulated cascode circuit according to aspects of the present invention.

FIG. 5 is a circuit diagram illustrating an example embodiment of a current mirror including a regulated cascode circuit according to aspects of the present invention.

FIG. 6 is a circuit diagram illustrating an example embodiment of an output stage of an amplifier including a regulated cascode circuit according to aspects of the present invention.

FIG. 7 is a graph illustrating a simulation result for comparing a regulated cascode circuit according to an example embodiment in accordance with aspects of the present invention with a conventional cascode circuit, as in FIG. 1.

Claims

1. A regulated cascode circuit comprising: a first MOS transistor of a first conductive type, coupled between an output node and a first node;a second MOS transistor of the first conductive type, coupled between the first node and a second power supply voltage, the second MOS transistor having a gate terminal configured to receive a bias voltage;a third MOS transistor of a second conductive type, coupled between a first power supply voltage and a gate terminal of the first MOS transistor;a first current source coupled between the gate terminal of the first MOS transistor and the second power supply voltage; anda second current source coupled between the first power supply voltage and the output node.

2. The regulated cascode circuit of claim 1, wherein a level of the first power supply voltage is higher than a level of the second power supply voltage, the first conductive type corresponds to N type, and the second conductive type corresponds to P type.

3. The regulated cascode circuit of claim 2, wherein a threshold voltage of the third MOS transistor is higher than a threshold voltage of the first MOS transistor and a threshold voltage of the second MOS transistor.

4. The regulated cascode circuit of claim 1, wherein a level of the first power supply voltage is lower than a level of the second power supply voltage, the first conductive type corresponds to P type, and the second conductive type corresponds to N type.

5. The regulated cascode circuit of claim 4, wherein a threshold voltage of the third MOS transistor is higher than a threshold voltage of the first MOS transistor and a threshold voltage of the second MOS transistor.

6. The regulated cascode circuit of claim 1, wherein a threshold voltage of the third MOS transistor is higher than a threshold voltage of the first MOS transistor and a threshold voltage of the second MOS transistor.

7. The regulated cascode circuit of claim 1, wherein a voltage difference between the first power supply voltage and the second power supply voltage is lower than about 1 volt.

8. The regulated cascode circuit of claim 1, wherein the third MOS transistor is body-biased to maintain a high threshold voltage.

9. A CMOS analog circuit comprising: a first current source coupled between a first power supply voltage and a first node;a first regulated cascode block coupled between the first node and a second power supply voltage, the first regulated cascode block configured to receive a voltage at the first node as a feedback bias voltage; anda second regulated cascode block coupled between an output node and the second power supply voltage, the second regulated cascode block configured to receive the voltage at the first node as a bias voltage and configured to mirror a current generated by the first current source, to output the mirrored current to the output node.

10. The CMOS analog circuit of claim 9, wherein the first regulated cacode block comprises: a first MOS transistor of a first conductive type, coupled between the output node and a second node;a second MOS transistor of the first conductive type, coupled between the second node and the second power supply voltage, the second MOS transistor having a gate terminal configured to receive the bias voltage;a third MOS transistor of a second conductive type, coupled between the first power supply voltage and a gate terminal of the first MOS transistor;a second current source coupled between the gate terminal of the first MOS transistor and the second power supply voltage; anda third current source coupled between the first power supply voltage and the output node.

11. The CMOS analog circuit of claim 10, wherein a level of the first power supply voltage is higher than a level of the second power supply voltage, the first conductive type corresponds to N type, and the second conductive type corresponds to P type.

12. The CMOS analog circuit of claim 11, wherein a threshold voltage of the third MOS transistor is higher than a threshold voltage of the first MOS transistor and a threshold voltage of the second MOS transistor.

13. The CMOS analog circuit of claim 10, wherein a level of the first power supply voltage is lower than a level of the second power supply voltage, the first conductive type corresponds to P type, and the second conductive type corresponds to N type.

14. The CMOS analog circuit of claim 13, wherein a threshold voltage of the third MOS transistor is higher than a threshold voltage of the first MOS transistor and a threshold voltage of the second MOS transistor.

15. The CMOS analog circuit of claim 10, wherein the second regulated cacode block comprises: a fourth MOS transistor of the first conductive type, coupled between the first node and a third node;a fifth MOS transistor of the first conductive type, coupled between the third node and the second power supply voltage, the fifth MOS transistor having a gate terminal configured to receive the bias voltage;a sixth MOS transistor of the second conductive type, coupled between the first power supply voltage and a gate terminal of the third MOS transistor; anda fourth current source coupled between the gate terminal of the third MOS transistor and the second power supply voltage.

16. The CMOS analog circuit of claim 9, wherein the second regulated cacode block comprises: a first MOS transistor of a first conductive type, coupled between the first node and a second node;a second MOS transistor of the first conductive type, coupled between the second node and the second power supply voltage, the second MOS transistor having a gate terminal configured to receive the bias voltage;a third MOS transistor of a second conductive type, coupled between the first power supply voltage and a gate terminal of the first MOS transistor; anda second current source coupled between the gate terminal of the first MOS transistor and the second power supply voltage.

17. The CMOS analog circuit of claim 9, wherein a level of the first power supply voltage is higher than a level of the second power supply voltage, the first conductive type corresponds to N type, and the second conductive type corresponds to P type.

18. A CMOS analog circuit comprising: a regulated cascode pull-up block coupled between a first power supply voltage and an output node, the regulated cascode pull-up block receiving a bias voltage; anda regulated cascode pull-down block coupled between the output node and a second power supply voltage, the regulated cascode pull-down block configured to receive an input voltage.

19. The CMOS analog circuit of claim 18, wherein the regulated pull-up block comprises: a first MOS transistor of a first conductive type, coupled between the first power supply voltage and a first node, the first MOS transistor having a gate terminal configured to receive a bias voltage;a second MOS transistor of the first conductive type, coupled between the first node and the output node, the second MOS transistor having a gate terminal coupled to a second node;a third MOS transistor of a second conductive type, coupled between the second node and the second power supply voltage, the third MOS transistor having a gate terminal coupled to the first node; anda first current source coupled between the first power supply voltage and the second node.

20. The CMOS analog circuit of claim 19, wherein the regulated pull-down block comprises: a fourth MOS transistor of the second conductive type, coupled between the output node and a third node, the fourth MOS transistor having a gate terminal coupled to a fourth node;a fifth MOS transistor of the second conductive type, coupled between the third node and the second power supply voltage, the fifth MOS transistor having a gate terminal configured to receive the input voltage;a sixth MOS transistor of the first conductive type, coupled between the first power supply voltage and the fourth node, the sixth MOS transistor having a gate terminal coupled to the third node; anda second current source coupled between the fourth node and the second power supply voltage.

21. The CMOS analog circuit of claim 18, wherein the regulated pull-down block comprises: a first MOS transistor of a first conductive type, coupled between the output node and a first node, the first MOS transistor having a gate terminal coupled to a second node;a second MOS transistor of the first conductive type, coupled between the first node and the second power supply voltage, the second MOS transistor having a gate terminal configured to receive the input voltage;a third MOS transistor of a second conductive type, coupled between the first power supply voltage and the second node, the third MOS transistor having a gate terminal coupled to the first node; anda first current source coupled between the second node and the second power supply voltage.