Patent Grant
7463013
This invention relates to regulated current mirror circuits and to integrated semiconductor devices having such circuits and methods of making and operating the same.
It is known to use current mirror circuits for various applications including current sources. These can be used for biasing of differential pairs, or for use in transconductance amplifiers and high speed digital receivers for example. There are many other applications of mirror circuits in analog low voltage or high voltage circuitry. As explained in U.S. Pat. No. 6,433,528, current mirrors replicate at their outputs the currents present at their inputs. There are many variations of the basic current mirror including regular cascode, high-swing cascode, regulated cascode, low voltage current, and active-input regulated cascode mirrors. U.S. Pat. No. 6,433,528 shows in FIG. 6 an example of a regulated cascode current mirror circuit, which uses an operational transconductance amplifier (OTA). A feedback path is provided and the OTA amplifies the difference between the feedback and a reference. Compliance voltage and output resistance are increased due to feedback. The compliance voltage is the output voltage range over which the current can be delivered accurately. But this and other prior art solutions have various disadvantages including lack of headroom, constrained operating characteristics, poor dynamics, and/or the need for OTAs which increase the surface of silicon (or in other words the transistor count) as well as the power dissipation.
To provide a high-impedance current source which has an optimized compliance enhanced operating characteristics and dynamics, and without using OTAs, U.S. Pat. No. 6,433,528 proposes a circuit shown in FIGS. 7 and 8 of U.S. Pat. No. 6,433,528 which uses two stages of current mirrors. As well as first and second current mirror stages, there is a stabilization circuit comprising two transistors coupled between the first and second current mirror stages, and an output circuit fed by the stabilization circuit, between the first and second current mirror stages. An advantage of this circuit is a low compliance voltage or point at which the circuit will operate, due to the feedback operation. This low compliance voltage allows headroom for other circuit operations. U.S. Pat. No. 6,433,528 relies on a regulator with a proportional action. System theory demonstrates that such a regulator used in the considered circuit can never achieve astatism of order 1.
There remains a need for devices with better precision for a given area, or reduced area for a given level of precision, particularly for high voltage applications.
An object of the invention is to provide improved apparatus or methods for regulated current mirror circuits and integrated semiconductor devices having such circuits and methods of making and operating the same.
The present invention can provide one or more of the following advantages compared with known devices:
a higher output resistance at low frequency,
a higher dynamic range at constant compliance and precision, i.e. that the ratio of output current to input current is relatively independent of the operating conditions,
the design is not determined by specific properties of the transistors, e.g. the sub-threshold properties of a transistor to sense variations of the output current, a reduction in the number of components, e.g. one current mirror instead of two.
According to a first aspect, the present invention provides a mirror current circuit comprising:
an output circuit including a transistor device to actuate the output current,
a regulator for controlling the output circuit,
a current mirror having two or more current paths,
The input current is a set-point signal for the mirror current circuit. The regulator generates a voltage applied to the gate of the transistor device of the output circuit. The regulator has integral action. The transistor device in the output circuit is preferably an MOS transistor.
Compared to known circuits without feedback, the feedback can provide better precision, or reduced component area, i.e. the MOS transistor in the output circuit can be chosen smaller, for a given precision. Compared to known two stage current mirror circuits, which have a feedback mirror circuit, this aspect differs in having the feedback mirror circuit being coupled in series with the output circuit.
An additional feature of the present invention is the current mirror comprising first and second transistors, the first transistor controlling the first current path, the second transistor controlling the second current path, control electrodes, e.g. gates, of the first and second transistors being coupled together. This arrangement enables the current paths to maintain the same or proportional currents. Also, in some embodiments, the second transistor is coupled between a supply line and an input line.
Another such additional feature is the mirror circuit being arranged such that the current in the second path is a proportion of the current in first path. This helps to decrease the total power dissipation.
Another additional feature for a dependent claim is bias current sources being coupled in each of the current paths. These enable the current mirror to be set up appropriately. Another such additional feature is cascode transistors connected in each of the current paths. This can provide a first level of precision for the mirror circuit and hence for the regulation of the output current.
Another such feature is a third transistor coupled to the control electrodes, e.g. gates of the current mirror to set a gate voltage. This can further improve precision.
Another such feature is the circuit being arranged such that in operation the first transistor is maintained close to a boundary between linear operation and saturation, to keep the voltage drop across the first transistor low. This can help optimize the compliance of the current source. This may be achieved by the third transistor and the fourth transistor being coupled in series in the first current path between the cascode transistor and the bias current source.
Another such feature is the third transistor being coupled in the first current path and the control electrodes, e.g. gates, of the current mirror being coupled to the first current path adjacent to the third transistor.
Another such feature is a fourth transistor coupled in the first current path and coupled to the control electrodes, e.g. gates, of the cascode transistors. This can further improve the precision of the current mirror and hence improve the regulation. This is used to determine the best gate voltages for the first and second transistors and the cascode transistors and hence to keep the first transistor at the border between linear operation and saturation.
Another such feature is the regulator having an integral action or control function, i.e. making an integration of a signal over time. This can be implemented by a capacitor. This can provide better regulation.
Another such feature is the output transistor being a MOS device, e.g. a DMOS device. This can enable high voltage operation. High voltage operation includes at least 25, 50, 80 and up to 120V.
Another aspect of the invention provides an integrated circuit having such a current mirror.
The present invention also includes a method of operating a mirror current circuit having a current mirror with two or more current paths, a first current path being coupled in series with an output circuit, the method comprising
actuating an output current of the output circuit by means of a transistor device,
Any of the additional features can be combined together and combined with any of the aspects. Other advantages will be apparent to those skilled in the art, especially over other prior art. Numerous variations and modifications can be made without departing from the claims of the present invention. Therefore, it should be clearly understood that the form of the present invention is illustrative only and is not intended to limit the scope of the present invention.
How the present invention may be put into effect will now be described by way of example with reference to the appended drawings, in which:
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. Any reference signs in the claims shall not be construed as limiting the scope of the invention. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.
The terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Furthermore, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
Moreover, it is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B. Where an indefinite or definite article is used when referring to a singular noun e.g. “a” or “an”, “the”, this includes a plural of that noun unless something else is specifically stated.
By way of introduction to the embodiments, a known arrangement will be described first, with reference to
An example of how this can be implemented is shown in
In operation, the transistor M3 will deliver a fixed current if its second main electrode voltage, e.g. drain voltage, is fixed to a stable value. In this circuit, this second main electrode voltage, e.g. drain voltage, is determined by transistor M4 in sub-threshold mode. By careful design, the saturation of transistor M3 can still be guaranteed even if both transistors M3 and M4 are tied to the same control electrode, e.g. gate. This can be achieved by a high W/L ratio of transistor M4 and setting a very low second main electrode current, e.g. drain current, on transistor M4. If the second main electrode voltage, e.g. drain voltage, of transistor M3 decreases (as a result of an increase in the output voltage Vout), the current through transistor M4 will diminish. This results in less current through the second current mirror stage comprised of transistors M2 and M5. The decreased current through transistor M2 causes the voltage at node V3 to increase and hence to increase at the control electrode, e.g. gate of output transistor M7 as well. This increase in control electrode voltage, e.g. gate voltage decreases the current flow through transistor M7, thus offsetting the effects of the increased output voltage. Therefore, any change on the second main electrode, e.g. drain, of transistor M3 due to the variation of the output voltage will be offset by operation of the second current mirror stage. Likewise, a decrease in the output voltage will be fed back through the second current mirror stage via transistor M4 and will result in a decreased control electrode voltage, e.g. gate voltage, on transistor M7. The decreased voltage on transistor M7 allows for increased current flow through transistor M7.
Quantitatively, the current is mainly determined by the mirror ratio between MOS transistors M1, M6, and M3. As explained above, the high stability in the output current Iout is obtained by tightly controlling the drain voltage of transistor M3, i.e. V2. Deriving a small part of the second main electrode current, e.g. drain current, of transistor M3 in a 1:1 NMOS second current mirror stage, comprised of transistors M5 and M2, provides the tight control of V2.
When the circuit is in balance, the percentage of transistor M3 second main electrode current, e.g. drain current flowing though transistors M4 and M5 is equal to the second main electrode current, e.g. drain current, of transistor M1. To get transistor M3 in saturation mode, this percentage and the size of M4 has to be chosen in such a way transistor M4 operates in the weak inversion region or in sub threshold mode. This means the current ratio between transistors M3 and M1 has to be very high to avoid excessively large dimensions for transistor M4. This scheme will fix the voltage V2 at the beginning of the saturation mode for transistor M3 and it will ensure a current proportional to the aspect ratios in transistors M6, M1, and M3.
Other aims for these embodiments include providing a large VGS, as large as possible for the output transistor (which has the consequence of decreasing Ron [on resistance] for a given size, or reducing size for a given Ron). The output transistor can be a DMOS transistor. The circuits also use as large a VDS as possible for the main mirror devices (which has the consequence that in saturation, it allows for larger threshold VT mismatch for a given accuracy or a higher accuracy for a given VT mismatch) and hence can improve accuracy. The feature of an integral type regulator may be credited for higher accuracy as well (beyond a conventional high precision mirror).
In
The current flowing through M1(201) is equal to IOut+αIBias. The current mirrored by M2(202) is equal to IOut/α+IBias. A current subtraction occurs at node N1, and the current IOut/α−IIn is integrated by the capacitor Ci (206). In some embodiments of the present invention, the capacitor Ci may be provided by the intrinsic capacitor between the control electrode and the first main electrode, e.g. a gate to source capacitor of output transistor MOut (205).
The voltage at node NG fed back to the control electrode, e.g. gate, of the transistor MOut will increase or decrease according to the sign of IOut/α−IIn, and by doing so will adjust the current IOut so as to satisfy the relation IOut=αIIn.
As discussed above, the regulated mirror current source 200 includes a feedback loop: the output current is fed back by the current mirror M1/M2 and compared to the command signal in the form of input current IIn. The error signal IIn−IOut/α is fed to the input of a regulator. The resulting signal is applied to the gate of transistor MOut, effectively closing a control loop. The regulator is effectively implemented by the arrangement of the subtraction of currents at N1 fed by the input current, and feedback current from M2 (202), and fed via cascade transistor M4 (204) to point NG. The regulator optionally includes an integral function, as implemented by the capacitor Ci illustrated.
In this case, transistors M5 (105) and M6 (106) are provided in series in the first current path between M3 and the bias current source. They serve to determine the gate voltages of transistors M1/M2 and M3/M4, as the gate of M1/M2 is coupled between M3 and M5 and the gate of M3/M4 is coupled between M5 and M6. This helps ensure that transistor M1(101) will be biased at the boundary between linear operation and saturation, (likewise for M3(103)), keeping the necessary voltage drop across the transistor M1(101) to a minimum and optimizing the compliance of the current source 100.
Operation of the circuit of
ID1=IOut+αIBias, αε0+ eq (1)
(most of the time αε|N0)0+ is the set of all non zero, positive real numbers
N0 is the set of all non-zero natural numbers (in other words non zero, positive integers)
ID2=(IOut+αIBias)/α eq (2)
ICi=sCi(VDD−V(NG)) where s is the Laplace variable
ICi=IBias−(IOut/α+IBias−IIn)=IIn−IOut/α
ΔV(NG)=−1/sCi(IIn−IOut/α)
IOut≈K′W/L)Out(V(N2)−V(NG)−VTh)2
W being the width of the transistor, L the length of the transistor and K′=½μCox the technological gain of the transistor
Hence,
ΔIOut≈−2 K′W/L)Out(V(N2)0−V(NG)0−VTh)ΔV(NG)
Or
ΔIOut≈−gmΔV(NG)
where gm is the transconductance of the transistor
Using the expression derived for ΔV(NG), it follows that:
ΔIOut/gm≈1/sCi(ΔIIn−ΔIOut/α).
Isolating ΔIOut, leads to
ΔIOut=gmαΔIIn/(gm+αCis)
The embodiments of the invention described show at least some of the following advantages:
The voltage drop being concentrated over transistor M1, the VDS of that transistor is maximized for every given output voltage. This allows operation with a gate overdrive as high as possible (while transistor M1 remains in saturation, i.e. VDS>VGS−VTh, the gate overdrive), which in turn guarantees the best matching possible in the M1/M2 (fluctuation in VTh will have an impact as low as possible). Indeed,
ΔID=−K′W/L(VGS−VTh)ΔVTh
and hence
ΔID/I=−2ΔVTh/(VGS−VTh)
which shows that the higher the gate voltage overdrive, the smaller the relative variation of ID will be.
Transistor MOut must not necessarily be in saturation, its VDS may be smaller than VDSSat=VGSOut−VTh since that transistor is not part of any mirror that requires precision. This means the gate voltage overdrive of the driver transistor can be maximised and guarantees a very low on-resistance. This property makes it possible to optimize either the Ron or the area of the output driver transistor. It also contributes in the optimization of the output compliance.
Although described for the case of high voltage circuits, using MOS transistors, e.g. DMOS transistors, it is applicable to low voltage circuits. The circuits can be implemented as integrated circuits, as part of much larger systems with many other circuit functions, as modules for application specific circuits, as hybrid circuits, or combinations of discrete components or in other forms for example. Other variations will be apparent to those skilled in the art and are intended to be within the scope of the claims.
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| 04078180 | Nov 2004 | EP | regional |
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| Number | Date | Country | |
|---|---|---|---|
| 20060113982 A1 | Jun 2006 | US |
