Patent Grant
8917231
The subject disclosure relates to displays and, more specifically, yet not exclusively, to control of gamma characteristic of a display having solid-state-based backlight illumination.
Backlights are used to illuminate liquid crystal displays (LCDs). LCDs with backlights are used in small displays for mobile phones, personal digital assistants (PDAs), portable computers, as well as in large displays for computer monitors and televisions. Often, the light source for the backlight includes one or more cold cathode fluorescent lamps (CCFLs). The light source for the backlight can also be an incandescent light bulb, an electroluminescent panel (ELP), or one or more hot cathode fluorescent lamps (HCFLs).
As costs of light emitting diodes (LEDs) are reduced and their quality is improved, the display industry is enthusiastically pursuing the use of light emitting diodes (LEDs) as the light source in backlight display technology because CCFLs have many shortcomings: For instance, CCFLs do not easily ignite in cold temperatures, they require adequate idle time to ignite, and they require delicate handling. In addition, LEDs have response times substantially faster than CCFLs. Moreover, the color gamut afforded by LEDs is wider than other light sources employed for backlighting and thus provide more vivid color. Furthermore, LEDs generally have a higher ratio of light generated to power consumed than other backlight sources. Accordingly, displays with LED backlights can consume less power than other displays, which renders LED-based displays more sustainable. LED backlighting has traditionally been used in small, inexpensive LCD panels. However, LED backlighting is becoming more common in large displays such as those installed in computers and television sets. In large LCD displays, several LEDs are generally required to provide adequate backlight for the LCD panel; based on specifics of the display, the number of LEDs can reach several hundreds.
Conventional displays such as those based on cathode ray tubes (CRTs) often have a fixed gamma characteristic which determines luminance of such displays. The gamma characteristic and thus the luminance is predetermined in accordance with a standard and generally suited for images that have been prepared for rendition in CRT-based displays. The gamma characteristic establishes a relationship amongst luminance (Ilum) of a display and backlight illumination intensity (IB) and magnitude (VD) of a signal related to data (e.g., an image data) to be displayed in the display. Typically, the relationship is a power relationship defined by a gamma value γ, such that I1um=κ(VD)γIB, where κ is an efficiency coefficient independent of γ. The gamma value γ thus defines the gamma characteristic. In an LCD display with LED-based backlighting, several LEDs utilized for backlighting can be partitioned into regions that span a display area of the LCD display. Brightness of at least one of such regions can change dynamically based on content (e.g., data) of an image to be rendered through pixel circuitry in the LCD display. Thus, utilization of a static gamma characteristic generally fails to provide adequate luminance for the LCD display because a static gamma characteristic cannot respond to changes in backlight brightness; low-quality rendered images thus ensues. While typical LCD displays can alter the gamma characteristic of a display on a frame-by-frame basis, such adjustment generally is insufficient for producing rich, compelling imagery.
The following presents a simplified summary of the subject disclosure in order to provide a basic understanding of some aspects thereof. This summary is not an extensive overview of the various embodiments of the subject disclosure. It is intended to neither identify key or critical elements nor delineate any scope. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
One or more embodiments of the subject disclosure provide system(s) and method(s) for controlling gamma characteristic of a display having LED-based backlight illumination. Controlling the gamma characteristic of such display can be accomplished at least in part through synchronization of data writing to a set of one or more pixels in a display within a video frame with backlight illumination of a region of the display during a predetermined period, wherein the region is spanned by the set of one or more pixels. Collection of data indicative of illumination intensity of light to be emitted in a region of a backlight source of the display during the predetermined period enables determination of at least one gamma value and at least one gamma reference voltage related to the at least one gamma value. Application of the at least one gamma reference voltage to the set of one or more pixels adjusts the gamma characteristic thereof within the video frame.
To the accomplishment of the foregoing and related ends, the one or more aspects include, without being limited to including, the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.
The subject disclosure is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It may be evident, however, that the various embodiments of the subject disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the present disclosure.
Backlight circuitry 250 illuminates pixel circuitry 240. Backlight circuitry 250 includes solid-state light source(s) 254 and a set of one or more driver(s) 258. As an example, solid-state light source(s) 254 are embodied in a set of one or more LEDs, which can be white LEDs, or LEDs emitting at multiple colors (e.g., red (R), green (G), blue (B) (RGB) LEDs, purple LEDs, orange LEDs . . . ), or a combination thereof. The set of one or more LEDs can be configured as a set of one or more strings of LEDs distributed throughout the display area of example display 200. Typically, each string is coupled to a power supply on one end and to the ground on the other end. One or more strings of LEDs can be associated with a single driver circuit of the set of one or more driver(s) 258. The driver circuit can control application of voltage or supply of current for the one or more strings of LEDs associated with the driver circuit. In certain embodiments, the association of the driver circuit and the one or more strings of LEDs is a one-to-one association. Accordingly, operation (e.g., on/off actuation) of each string can be manipulated independently through the associated driver. For instance, each LED string can be selectively turned on and off for providing localized dimming, or for producing disparate white color of different temperatures. Generally, each string of LEDs includes a group of the LEDs of the same type (e.g., RGB LEDs) to improve uniformity of operational characteristics, such temperature coefficients, I-V characteristics, or the like, and thus enhance control performance of each string of LEDs. LEDs in a string of LEDs of a set of one or more strings of LEDs that can part of backlight circuitry 250 can be discretely scattered across an electronic display and connected in series by wires, traces or other connecting elements. As an example, the LEDs in the set of one or more strings of LEDs can be arranged in vertical fashion or in other arrangements, such as in a horizontal configuration. Moreover, LED strings can be mutually parallel or can be deployed in other relative orientations.
Through disparate organization the set of one or more strings of LEDs, a backlighting area can be partitioned into various zones, as illustrated in
Diagrams 306 and 308 present partitions in four and 16 tiles, respectively. In particular, though not exclusively, phase delays and duty cycles for backlight illumination can vary from tile to tile. Moreover, gamma regulation component 218 can be functionally coupled to a set of one or more driver circuits that enable to configure disparate subsets of pixel columns in the K×J pixel matrix structure. In certain embodiments, the set of one or more drivers can be part of image controller 214. In additional or alternative embodiments, such set of one or more drivers can be included in gamma regulation component 218. In an aspect, the larger the number P of zones in which the display area is divided, the higher the efficiency of the display with respect to duty cycle of the backlight unit (e.g., a set of one or more LED strings and associated driver(s)) in the display.
As part of regulation of operation of pixel circuitry 240, image controller 214 receives data, e.g., image data 204, and supplies the data to the pixel circuitry 240. To supply the data, image controller 214 can write the data into each pixel in a line-by-line manner, or scrolling motion; data is written in a pixel by charging the capacitor that is part of the pixel. Image controller 214 can include at least one digital-to-analog converter (DAC) to charge the capacitor based at least on the data intended to or available for the pixel. Diagram 400 in
In an aspect, to scan the group of K×J pixels that can be part of pixel circuitry 240, and write data to such pixels on a line-by-line basis, image controller 214 can exploit timing signal generator 222. Timing signal generator 222 can produce clock signals that enable image controller 214 to scan the group of K×J pixels. The clock signals can include vertical synchronization (VSYNC) signal, horizontal synchronization (HSYNC) signal, gate shift clock (GSC) signal, and so forth. Timing signal generator 112 also can multiply the frequency of the clock signals to generate timing signals with higher frequency. Through multiplication of the frequency of at least one of the clock signals, the timing signal generator 112 can produce a timing signal that defines a sub-frame period for scanning a group of pixels that is part of a line of pixels in pixel circuitry 240. Moreover, timing signal generator 112 can scale (or divide) the amplitude of one or more of the clock signals.
Additionally, in order to mitigate blur artifacts due to rapidly changing image(s) and improve motion picture response, display controller 210 can illuminate pixel circuitry 240 in a lagging scrolling motion fashion through backlight circuitry 250. Diagram 440 in
As described previously and illustrated in diagram 480 in
To adjust a gamma value within a video frame (e.g., 404U), the gamma regulation component 218 can apply a reference voltage (VRef) to a driver circuit that generates the reference voltage in the transistor present in a pixel. For a pixel that has a Red sub-pixel, a Green sub-pixel, and a Blue sub-pixels, a gamma reference voltage VRef(Red)(γ), a gamma reference voltage VRef(Green) (γ), and a gamma reference voltage VRef(Blue)(γ) are applied to the pixel, respectively. In general, for a pixel that includes a set of one or more colored LEDs emitting respectively at colors v1, v2, v3 . . . vs, a set of one or more gamma reference voltages for each color—VRef(v
In an aspect, gamma regulation component 218 establishes (computes, receives, retrieves, etc.) a gamma value γ based on a function F(t, R; IB (R)) and acquires (receives, retrieves, etc.) at least one gamma reference voltage (e.g., VRefv
Diagram 500 in
It should be appreciated that illumination intensity at a region boundary is not abrupt due to overlap at region edges of adjacent regions. Such overlap is a result of the smaller density of solid-state light source elements (e.g., strings of LEDs) in backlight circuitry 250 with respect to density of pixels in pixel circuitry 240. Accordingly, a transition region that spans one or more pixel lines generally is present amongst two adjacent regions; in the transition region, a first backlight illumination intensity in a first region gradually transitions, or fades, to a second backlight illumination intensity in a second region. Specific number of pixel lines in such transition region is dictated, at least in part, by the topology, or physical arrangement, of the solid-state light source elements (e.g., strings of LEDs) in backlight circuitry 250. Diagram 700 in
In an aspect, gamma values γK and γJ are associated, respectively, with gamma reference voltages VK and VJ. In diagram 750, Q0=7 gamma values span the transition region 710, such values can correspond to Q0=7 pixel lines present in the transition region 710. It should be readily appreciated that the transition region 710 can span Q pixel lines, with Q a natural number greater than or equal to unity (1), and Q intermediate gamma reference voltages {V1, V2 . . . VQ−1, VQ} associated with intermediate gamma values can be implemented. In an aspect, configuration of such gamma reference voltages is effected on a line-by-line basis. To at least that end, in an example embodiment, gamma regulation component 218 can configure an intermediate gamma value (e.g., apply an intermediate gamma reference voltage) during a horizontal blanking period configured for example display 200 (or any display that includes the gamma regulation component 218). Configuration of a gamma value during such blanking interval mitigates or completely avoids image disturbances that can arise from driving the transistor associated with the line of pixel(s) in a transition region. As part of configuration of the intermediate gamma reference voltages, gamma regulation component 218 can access a memory included therein or functionally coupled thereto, wherein the memory has stored, or programmed, thereon the Q intermediate gamma reference voltages {V1, V2 . . . VQ−1, VQ}, with Q a natural number.
In certain embodiments gamma regulation component 218 also can adjust gamma values in alternative partitions of a display area (see, e.g.,
In response to signaling and related payload data received from sync component 814, reference voltage generator 818 can collect a group of gamma value(s) from the set 826 of one or more gamma values and configure a group of gamma reference voltage(s). Reference voltage generator 818 can apply the group of gamma reference voltage(s) to the group of pixels in the first region. In aspect, the set 826 of one or more gamma values can be part of the one or more register(s) 237. The group of gamma reference voltage(s) is applied before or upon the second counter reaches a threshold counts that convey that HSYNC interval has elapsed. In a scenario in which white LEDs embody the solid-state light source(s) 254, the group of gamma reference voltage(s) has at least one gamma reference voltage VRef (γ). In an alternative scenario in which RGB LEDs embody the solid-state light source(s) 254, the group of gamma reference voltage(s) has at least three gamma reference voltages: VRef(Red)(γr), VRef(Green)(γG), and VRef(Blue)(γB). In another alternative scenario, when a set of one or more LEDs of multiple colors v1, v2, v3 . . . vC embodies the solid-state light source(s) 254, the group of gamma reference voltage(s) has at least C gamma reference voltages values VRef(v
As discussed above, gamma regulation component 218 can enable “fading”, or gradual transition, of gamma values amongst two gamma values associated with respective two adjacent regions (e.g., Region I and Region II, or Region V′ and Region VI′) of a display area. In an aspect, to implement such “fading”, gamma regulation component 218 can include a fade component 822 that is configured (e.g., programmed) with an offset value δ=2×nΔ+1 that represents a number of pixel lines spanned by a transition region (e.g., as illustrated by transition region 710) that separates two adjacent regions (e.g., Region K 706 and Region J 714). In addition, fade component 822 also receives timing signal(s) for a counter nL, from sync component 814 and initiates a transition counter nT upon or substantially at a time after the last line nL=W−nΔ−1 of a first region has been written; W is a natural number. Counter nL, continues to accrue counts as a result of data being written to lines of pixels in the transition zone. Counter nL, is synchronized with counter nT; however, at each increment of counter nT by 1, e.g., after a line of pixels in the transition zone is written completely, reference voltage generator 818 extracts a fade gamma value determined by at least one fade scale in the set 828 of one or more fade scale(s) and configures a fade gamma reference voltage that corresponds to the fade gamma value. In aspect, the set 828 of one or more fade scale(s) can be part of the one or more register(s) 237. As indicated previously, a set of Q fade gamma reference voltage values {V1, V2 . . . VQ-1, VQ} can be retained in the set 828 of one or more fade scale(s). As an alternative, a single voltage offset ΔV can be retained in memory 238 in conjunction with a logical variable that indicates that fade gamma reference values can be generated through the recursion Vω+1−Vω=ΔV, with ω=1, 2, . . . , Q, and ΔV=γK−γJ. As described above, reference voltage generator 818 applies the fade gamma reference voltage during the horizontal write blanking period (HSYNC) of the display that includes gamma regulation component 218. Accordingly, in an aspect, gamma regulation component 218 adjusts the gamma characteristic of the transition region (e.g., 710) on a line-by-line basis.
In example display 200, to implement the various features or aspects described in the foregoing passages, display controller 210 can include one or more processor(s) 234. In addition, input/output (I/O) component(s) (not shown) can enable configuration of various registers and other values utilized in operation of display controller 210. In an aspect, the one or more processor(s) 234 can enable or be configured to enable, at least in part, the described functionality of display controller 210 or one or more functional elements (e.g., component(s), generator(s), block(s), module(s)) therein. In an aspect, to provide such functionality, the one or more processor(s) 234 can exploit a bus architecture 235 to exchange data or any other information amongst functional elements (e.g., component(s), controller(s), generator(s), blocks) within display controller 210 and a memory 238 functionally coupled thereto. The bus architecture 235 can be embodied in at least one of a memory bus, a system bus, an address bus, a message bus, a set of one or more pins, or any other conduit, protocol, or mechanism for data or information exchange among components that execute a process or are part of execution of a process. The exchanged information can include at least one of code instructions, code structure(s), data structures, or the like.
The one or more processor(s) 234 also can execute computer-executable instructions (not shown) stored in memory 238 to implement (e.g., execute) or provide at least part of the described functionality of display controller 210. Such code instructions can include program modules, software applications, or firmware applications that implement specific tasks which can be accomplished, for example, through one or more of the methods disclosed herein and that are associated, at least in part, with functionality or operation of example display 200. In one or more alternative or additional embodiment(s), the one or more processor(s) 234 can be distributed amongst one or more functional elements (components, blocks, etc.) of display controller 210.
In one or more embodiments, display controller 210 can be either a general microcomputer or a special purpose microcomputer. Display controller 210 and other component(s) or functional element(s) can be implemented on a single integrated circuit (IC) chip or on multiple IC chips. ICs can include at least one processor, which can be part of processor(s) 234. In embodiments including multiple IC chips, functional elements of display controller 210 can be arranged in modules, wherein in each module is implemented in an IC. In addition, through provision of computer-executable instructions to a memory functionally coupled to the display controller 210 or included therein, display controller 210 can be programmable. In the alternative, display controller 210 can be non-programmable and operate in accordance with aspects herein as established at manufacturing time. In a combined approach, certain features of display controller 210 can be programmable while others can be non-programmable and preserved as provisioned at manufacturing time. Display controller 210 or one or more components therein can be implemented in hardware, software, or firmware.
In view of the example system(s) described above, example methods that can be implemented in accordance with the disclosed subject matter can be better appreciated with reference to flowchart in
Method(s) disclosed throughout the subject specification and annexed drawings are capable of being stored on an article of manufacture to facilitate transporting and transferring such method(s) to computers or chipsets, e.g., integrated semiconductor-based circuits, with processing capability(ies) for execution, and thus implementation, by a processor, or for storage in a memory. In an aspect, one or more processors that enact method(s) described herein can be employed to execute code instructions retained in a memory, or any computer- or machine-readable storage medium, to implement method(s) described herein; the code instructions, when executed by the one or more processor implement or carry out the various acts in the method(s) described herein. The machine-executable or computer-executable instructions provide a machine-executable or computer-executable framework to enact (e.g., execute) the method(s) described herein.
At act 940, based at least on one or more of the illumination intensity or the pixel content, a gamma characteristic of the set of one or more pixels of the display is adjusted. The gamma characteristic is adjusted in response to the first period elapsing. In an aspect, the gamma characteristic can be adjusted upon or at substantially the instant at which the first period elapses. In another aspect, the gamma characteristic can be adjusted at a predetermined interval subsequent to the first period elapsing. Adjusting the gamma characteristic includes updating the gamma characteristic during a horizontal blanking period (determined by an HSYNC clock signal) of the display. Updating the gamma characteristic includes determining at least one gamma value and configuring at least one gamma reference voltage corresponding to the gamma value. The adjusting also includes applying the at least one gamma reference voltage to each pixel in the set of one or more pixels. Determining a gamma value can include computing the gamma value through a first predetermined function of the illumination intensity, a second predetermined function of the pixel content, or a third function of the illumination content and pixel content (or pixel data). In the alternative, to reduce complexity and processing load (e.g., number of operations performed by processor(s) 234) determining the gamma value can include acquiring the gamma value from a look-up table retained in a buffer (e.g., memory 234) or one or more memory elements therein (register(s), such as register(s) 237; databases; file(s); etc.). The look-up table can be constructed via the first predetermined function, the second predetermined function, or the third predetermined function. Various look-up tables can be defined and retained in the buffer.
At act 950, light is emitted in the region of the backlight source at the illumination intensity during the second period. In an embodiment, the second period commences after a predetermined interval elapses from initiation of the first period for data writing. For example, for a null or substantially null predetermined interval, the second period and the first period can be concurrent or substantially concurrent. For another example, the magnitude of the predetermined interval causes the second period and the first period to overlap partially. Yet in another example, the magnitude of the predetermined interval causes the second period to be disjoint with the first period, wherein the commencement instant for the second period is a predetermined lag phase (see, e.g.,
At act 1130, for each pixel line in the set of one or more pixel lines, a gamma characteristic of at least one pixel in a current pixel line is adjusted in response to completion of writing data to the current line. The gamma characteristic can be adjusted during a horizontal blanking interval (HSYNC). Adjusting the gamma characteristic can include generating a gamma value for the current line of pixels and, and in response, configuring a gamma reference voltage related (in a one-to-one relationship, for example) to the gamma value. In an aspect, generating such gamma value can be accomplished by computing the gamma value, by reading a look-up table in a memory element (e.g., register). Additionally or alternatively, generating the gamma value can be accomplished by querying a component data manages content of a buffer functionally coupled to the gamma regulation module that implements the subject example method. In certain embodiments, the gamma value can be constant (Δγ) for each pixel line in the set of one or more pixel lines, and it can be applied as an offset a previous gamma value: For cardinality C0, γκ+1−γκ=Δγ, with κ=1, 2, . . . , C0, and Δγ=γII−γI where γI is the gamma value corresponding to the first region and γII is the gamma value corresponding to the second region. For each value γκ, a related gamma reference voltage Vκ is configured.
By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which acts as external cache memory. By way of further illustration and not limitation, RAM can be available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct Rambus RAM (DRRAM). Additionally, the disclosed memory components of systems or methods herein are intended to include, without being limited to including, these and any other suitable types of memory.
The various illustrative logics, logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a group of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Additionally, at least one processor may include, without limited to including, one or more modules operable to or configured to perform one or more of the steps or acts described above.
Further, the steps or acts of a method or algorithm described in connection with the aspects disclosed herein may be embodied directly in hardware; in a software module executed by a processor; or in a combination of the two, such as in a firmware module. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium may be coupled to the processor, such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. Further, in some aspects, the processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in display equipment. In the alternative, the processor and the storage medium may reside as discrete components, e.g., chipsets, in display equipment. Additionally, in some aspects, the steps or acts of a method or algorithm may reside as one or any combination or set of one or more codes or instructions on a machine-readable medium or computer-readable medium, which may be incorporated into a computer program product.
In one or more aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium or machine-readable medium. Computer-readable media machine-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include, without limited to including, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection may be termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs usually reproduce data optically with lasers. Combinations of the above also are included within the scope of computer-readable media.
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| Number | Date | Country | |
|---|---|---|---|
| 20120154462 A1 | Jun 2012 | US |
