Patent Application
20230018651
This application claims priority benefit of Japanese Patent Application No. JP 2021-118077 filed in the Japan Patent Office on Jul. 16, 2021. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.
The present disclosure relates to a regulator circuit.
A regulator circuit that generates a stable voltage with a small voltage change is used in various electronic devices, such as consumer products including a smartphone and a tablet computer, in-vehicle devices, office automation (OA) equipment, and industrial equipment. The regulator circuit is broadly classified into a switching regulator and a linear regulator circuit.
Feedback by an error amplifier stabilizes the output voltage of the regulator circuit at a target level. Phase compensation may be necessary for stable operation of the regulator circuit without oscillation.
ωp=1/(Cout·Rout) (1)
Cout represents a capacitance of the output capacitor 16, and Rout represents an impedance of the load 20.
A phase compensation circuit is implemented in the error amplifier 12 to cancel the influence of the pole ωp. The phase compensation circuit adds zero to an appropriate position with respect to a certain pole ωp to prevent a phase lead.
The same applies to the switching regulator, and the phase compensation circuit is implemented in the error amplifier.
An example of the related art is disclosed in PCT Patent Publication No. WO2021/124910.
As can be understood from Equation (1), the pole frequency ωp is dependent on the load impedance. Accordingly, the pole frequency ωp changes in an application with a dynamically changing load impedance. In such a case, the circuit constants of the phase compensation circuit may need to be determined to satisfy the stability conditions for all assumed poles ωp, making it difficult to design the circuit.
According to an embodiment of the present disclosure, it is desirable to provide a regulator circuit or a control circuit of a direct current/direct current (DC/DC) converter capable of performing stable operation with respect to a dynamically changing load.
A mode of the present disclosure relates to a regulator circuit that supplies an output voltage to a load. The regulator circuit includes an error amplifier that amplifies an error between a feedback signal corresponding to the output voltage and a reference voltage, and an output stage that changes the output voltage according to an output of the error amplifier. The error amplifier includes a first transconductance amplifier that receives the feedback signal and the reference voltage, a first resistance connected to an output node of the first transconductance amplifier and a ground, a first capacitor connected in parallel to the first resistance, a second transconductance amplifier that receives a voltage of the output node of the first transconductance amplifier and the feedback signal, a second resistance connected to an output node of the second transconductance amplifier and a ground, a second capacitor connected in parallel to the second resistance, and a zero controller that controls a gain of the second transconductance amplifier according to an output current of the regulator circuit.
Another mode of the present disclosure also provides a regulator circuit. The regulator circuit includes an error amplifier that amplifies an error between a feedback signal corresponding to an output voltage and a reference voltage, and an output stage that changes the output voltage according to an output of the error amplifier. The error amplifier includes a first amplifier of a high-gain narrow-band and a second amplifier of a low-gain broadband that are connected in cascade, and a zero controller that controls a gain of the second amplifier according to an output current of the regulator circuit.
Yet another mode of the present disclosure relates to a control circuit of a DC/DC converter. The control circuit includes an error amplifier that amplifies an error between a feedback signal corresponding to an output voltage of the DC/DC converter and a reference voltage, and a pulse modulator that generates a pulse signal according to an output of the error amplifier. The error amplifier includes a first transconductance amplifier that receives the feedback signal and the reference voltage, a first resistance connected to an output node of the first transconductance amplifier and a ground, a first capacitor connected in parallel to the first resistance, a second transconductance amplifier that receives a voltage of the output node of the first transconductance amplifier and the feedback signal, a second resistance connected to an output node of the second transconductance amplifier and a ground, a second capacitor connected in parallel to the second resistance, and a zero controller that controls a gain of the second transconductance amplifier according to an output current of the DC/DC converter.
Yet another mode of the present disclosure also provides a control circuit of a DC/DC converter. The control circuit includes an error amplifier that amplifies an error between a feedback signal corresponding to an output voltage of the DC/DC converter and a reference voltage, and a pulse modulator that generates a pulse signal according to an output of the error amplifier. The error amplifier includes a first amplifier of a high-gain narrow-band and a second amplifier of a low-gain broadband that are connected in cascade, and a zero controller that controls a gain of the second amplifier according to an output current of the DC/DC converter.
Note that any combinations of the constituent elements as well as constituent elements and expressions obtained by exchanging the constituent elements and the expressions among methods, apparatuses, and systems are also effective as modes of the present technology.
According to the modes of the present disclosure, the stability of the regulator circuit can be improved.
An overview of some exemplary embodiments of the present disclosure will be described. The overview briefly describes some concepts of one or a plurality of embodiments for basic understanding of the embodiments as a preface to detailed explanation described later, and the overview does not limit the extent of the technology or the disclosure. The overview is not a comprehensive overview of all possible embodiments, and the overview is not intended to specify important elements of all the embodiments or to define the scope of part or all of the modes. For convenience, “one embodiment” may be used to represent one embodiment (example or modification) or a plurality of embodiments (examples or modifications) disclosed in the present specification.
A regulator circuit according to an embodiment supplies an output voltage to a load. The regulator circuit includes an error amplifier that amplifies an error between a feedback signal corresponding to the output voltage and a reference voltage, and an output stage that changes the output voltage according to an output of the error amplifier. The error amplifier includes a first transconductance amplifier that receives the feedback signal and the reference voltage, a first resistance connected to an output node of the first transconductance amplifier and a ground, a first capacitor connected in parallel to the first resistance, a second transconductance amplifier that receives a voltage of the output node of the first transconductance amplifier and the feedback signal, a second resistance connected to an output node of the second transconductance amplifier and a ground, a second capacitor connected to the output node of the second transconductance amplifier, in parallel to the second resistance, and a zero controller that controls a gain of the second transconductance amplifier according to an output current of the regulator circuit.
In a regulator circuit with constant voltage output, the output current of the regulator circuit is inversely proportional to the impedance of the load. The pole shifts to the low frequency side when the impedance of the load becomes large. In this case, the output current decreases, and the gain of the second transconductance amplifier can be increased accordingly to shift the zero point of the error amplifier to the low frequency side. This allows adaptive phase compensation according to the load change.
In an embodiment, the zero controller may successively change a bias current of the second transconductance amplifier according to the output current of the regulator circuit. The bias current can be successively changed to successively move the zero point in association with the pole.
In an embodiment, the smaller the output current of the regulator circuit is, the more the zero controller may increase the bias current of the second transconductance amplifier.
In an embodiment, the regulator circuit may be a linear regulator circuit. The output stage may include an output transistor. The zero controller may include a first transistor with a gate and a source connected in common to a gate and a source of the output transistor, and a correction current generation circuit that generates a correction current corresponding to a current flowing through the first transistor and that supplies the correction current to the second transconductance amplifier.
In an embodiment, the regulator circuit may be a DC/DC converter. The zero controller may change the bias current of the second transconductance amplifier according to an output current of the DC/DC converter when the DC/DC converter operates in a discontinuous conduction mode.
A regulator circuit according to an embodiment includes an error amplifier that amplifies an error between a feedback signal corresponding to an output voltage and a reference voltage, and an output stage that changes the output voltage according to an output of the error amplifier. The error amplifier includes a first amplifier of a high-gain narrow-band and a second amplifier of a low-gain broadband that are connected in cascade, and a zero controller that controls a gain of the second amplifier according to an output current of the regulator circuit. Here, the high gain and the low gain are relative, and the narrow band and the broadband are relative.
In this configuration, the pole of the first amplifier and the pole of the second amplifier are combined, and the frequency characteristics of the error amplifier include pseudo one pole and one zero. The zero point shifts to the low frequency side when the gain of the second amplifier of the low-gain broadband is increased. The zero point shifts to the high frequency side when the gain of the second amplifier is reduced. Therefore, the zero point can be shifted in association with the movement of the pole associated with the load change.
In an embodiment, the second amplifier may include a second transconductance amplifier, a second resistance connected to an output node of the second transconductance amplifier, and a second capacitor connected in parallel to the second resistance.
In an embodiment, the zero controller may control a gain of the second transconductance amplifier according to the output current of the regulator circuit.
In an embodiment, the zero controller may control an impedance of the second resistance according to the output current of the regulator circuit.
In an embodiment, the regulator circuit may be integrated into one semiconductor substrate. The “integration” includes a case in which all of the constituent elements of the circuit are formed on the semiconductor substrate and a case in which main constituent elements of the circuit are integrated. Some of resistances, capacitors, and other constituent elements for adjusting the circuit constants may be provided outside the semiconductor substrate. Integrating the circuit on one chip allows the circuit area to be reduced and the characteristics of the circuit elements to be kept uniform.
A control circuit of a DC/DC converter according to an embodiment includes an error amplifier that amplifies an error between a feedback signal corresponding to an output voltage of the DC/DC converter and a reference voltage, and a pulse modulator that generates a pulse signal according to an output of the error amplifier. The error amplifier includes a first transconductance amplifier that receives the feedback signal and the reference voltage, a first resistance connected to an output node of the first transconductance amplifier and a ground, a first capacitor connected in parallel to the first resistance, a second transconductance amplifier that receives a voltage of the output node of the first transconductance amplifier and the feedback signal, a second resistance connected to an output node of the second transconductance amplifier and a ground, a second capacitor connected in parallel to the second resistance, and a zero controller that controls a gain of the second transconductance amplifier according to an output current of the DC/DC converter.
In a DC/DC converter with constant voltage output, the output current of the DC/DC converter is inversely proportional to the impedance of the load. The pole shifts to the low frequency side when the impedance of the load becomes large. In this case, the output current decreases, and the gain of the second transconductance amplifier can be increased accordingly to shift the zero point of the error amplifier to the low frequency side. This allows adaptive phase compensation according to the load change.
A control circuit of a DC/DC converter according to an embodiment includes an error amplifier that amplifies an error between a feedback signal corresponding to an output voltage of the DC/DC converter and a reference voltage, and a pulse modulator that generates a pulse signal according to an output of the error amplifier. The error amplifier includes a first amplifier of a high-gain narrow-band and a second amplifier of a low-gain broadband that are connected in cascade, and a zero controller that controls a gain of the second amplifier according to an output current of the DC/DC converter.
In this configuration, the pole of the first amplifier and the pole of the second amplifier are combined, and the frequency characteristics of the error amplifier include pseudo one pole and one zero. The zero point shifts to the low frequency side when the gain of the second amplifier of the low-gain broadband is increased. The zero point shifts to the high frequency side when the gain of the second amplifier is reduced. Thus, the zero point can be shifted in association with the movement of the pole associated with the load change.
The present disclosure will now be described in reference to preferred embodiments and the drawings. The same signs are provided to the same or equivalent constituent elements, members, and processes illustrated in the drawings, and duplicate description will appropriately be omitted. The embodiments are exemplary, and not intended to limit the technology or the disclosure. All features and combinations of the features described in the embodiments may not necessarily be essential for the technology or the disclosure.
In the present specification, “a state in which a member A and a member B are connected” includes a case in which the member A and the member B are physically and directly connected as well as a case in which the member A and the member B are indirectly connected through another member that does not substantially affect their electrical connection state and that does not impair the functions and the effects obtained by the coupling of them.
Similarly, “a state in which a member C is provided between a member A and a member B” includes a case in which the member A and the member C or the member B and the member C are directly connected as well as a case in which they are indirectly connected through another member that does not substantially affect their electrical connection state and that does not impair the functions and the effects obtained by the coupling of them.
The load 202 is connected to an output line of the regulator circuit 100. The regulator circuit 100 supplies the load 202 with an output voltage VOUT stabilized at a predetermined voltage level VOUT(REF). The regulator circuit 100 may be a linear regulator or may be a DC/DC converter (switching regulator).
The regulator circuit 100 includes an error amplifier 110, an output stage 120, resistances R11 and R12, and an output capacitor C11.
The output voltage VOUT is divided by the resistances R11 and R12, and a feedback signal VFB is generated. The error amplifier 110 amplifies an error between the feedback signal VFB and a reference voltage VREF. The output stage 120 steps down or steps up an input voltage VIN according to an output VERR of the error amplifier 110 to change the output voltage VOUT. The output stage 120 has a configuration or topology corresponding to the type of regulator circuit 100.
The output voltage VOUT is stabilized at the following target level VOUT(REF) when the feedback loop is stable.
V
OUT(REF)
−V
REF×(R11+R12)/R12
The error amplifier 110 includes a first amplifier AMP1, a second amplifier AMP2, and a zero controller 130 that are connected in cascade. The first amplifier AMP1 is designed to correspond to a relatively high gain narrow-band, and the second amplifier AMP2 is designed to correspond to a relatively low gain broadband. The gains of the first amplifier AMP1 and the second amplifier AMP2 will be referred to as g1 and g2, respectively.
This completes the description regarding the configuration of the regulator circuit 100. Next, an operation of the regulator circuit 100 will be described.
A pole ωp2 formed by the load 202 and the output capacitor C11 shifts to the low frequency side when the output current IOUT decreases, in other words, when a load impedance Rout increases. A phase margin can be reserved by shifting of the zero point ωz of the error amplifier 110 in association with the shift of the pole ωp2.
The present disclosure applies to various apparatuses and methods figured out as the block diagram or the circuit diagram of
Alternatively, the semiconductor chip 300A may be a general functional IC including a linear regulator, and in that case, the load 202 is integrated into the semiconductor chip 300A.
An error amplifier 110A and an output stage 120A are integrated into the semiconductor chip 300A. The output stage 120A includes an output transistor M11. Although the output transistor M11 is a P-channel metal oxide semiconductor field effect transistor (MOSFET) in the present embodiment, the output transistor M11 is not limited to this. The output transistor M11 may be an N-channel MOSFET or may be a PNP or NPN bipolar transistor. The output transistor M11 may be an external discrete element connected to the semiconductor chip 300A.
The error amplifier 110A generates the error voltage VERR to bring the feedback signal VFB into line with the reference voltage VREF and supplies a gate voltage VG corresponding to the error voltage VERR to the gate of the output transistor M11. Although the error voltage VERR is directly input to the gate of the output transistor M11 in
The second transconductance amplifier 114 receives a voltage VAMP1 of the output node of the first transconductance amplifier 112 and the feedback signal VFB. The second resistance R22 is connected to the output node of the second transconductance amplifier 114 and the ground. The second capacitor C22 is connected to the output node of the second transconductance amplifier 114 and the ground, in parallel to the second resistance R22. The second transconductance amplifier 114, the second resistance R22, and the second capacitor C22 correspond to the second amplifier AMP2 of
As described above, the zero controller 130A controls the gain g2 of the second amplifier AMP2 corresponding to the low-gain broadband, according to the output current IOUT of the regulator circuit 100. In
The zero controller 130A successively changes the bias current IBIAS generated by the bias current source CS21, according to the output current IOUT of the linear regulator circuit 100A. The bias current IBIAS can be successively changed to successively move the zero point in association with the pole.
The zero controller 130A controls the bias current source CS21 such that the smaller the output current IOUT of the regulator circuit 100 is, the more the bias current IBIAS will increase. The bias current IBIAS can be changed to change the gain of the differential amplifier 116 and eventually the transconductance gm2 of the second transconductance amplifier 114.
The second transconductance amplifier 114 can further include an amplification stage 118 provided on a later stage of the differential amplifier 116. In this case, the bias current IBIAS to be supplied to the amplification stage 118 can also be changed in conjunction with the bias current IBIAS of the differential amplifier 116.
In a case where the linear regulator circuit 100A is a low drop output (LDO) in which the potential of the input voltage VIN and the output voltage VOUT is significantly small, the output transistor M11 operates in a linear region with a significantly small drain-source voltage, and the difference between the drain-source voltage of the output transistor M11 and the drain-source voltage of the transistor M12 becomes large.
In that case, the zero controller 130A can include a stabilization circuit 132. The stabilization circuit 132 is designed such that the drain voltage of the transistor M12 becomes equal to the drain voltage (that is, output voltage VOUT) of the output transistor M11. The stabilization circuit 132 includes, for example, a transistor M13 and an error amplifier 134, and the error amplifier 134 adjusts the gate voltage of the transistor M13 such that a drain voltage VD of the transistor M12 becomes equal to the output voltage VOUT. In the case of LDO, an adjustment current IADJ proportional to the output current IOUT can be obtained by the stabilization circuit 132 being added.
The bias current source CS21 includes, for example, a constant current source 150 that generates a constant current Ic. Connecting the output of the zero controller 130A to the bias current source CS21 allows the difference between the constant current Ic and the adjustment current IADJ to be supplied as the bias current IBIAS to the differential amplifier 116 and the amplification stage 118. The bias current IBIAS increases when the adjustment current IADJ decreases after a decrease in the output current IOUT. On the other hand, the bias current IBIAS decreases when the adjustment current IADJ increases after an increase in the output current IOUT.
The configuration of the zero controller 130A and the bias current source CS21 is not limited to the configuration illustrated in
The controller IC 300B includes an input pin VIN, a switching pin SW, a ground pin GND, and a feedback pin FB. An inductor L11 is connected to the switching pin SW.
The controller IC 300B includes an error amplifier 110B, a pulse modulator 122, a driver 124, a high side transistor MH, and a low side transistor ML. The pulse modulator 122, the driver 124, the high side transistor MH, the low side transistor ML, and the external inductor L11 correspond to the output stage 120 illustrated in
The error amplifier 110B includes the first amplifier AMP1, the second amplifier AMP2, and a zero controller 130B that are connected in cascade.
The pulse modulator 122 generates a pulse signal Sp corresponding to the output VERR of the error amplifier 110B. The pulse modulator 122 is, for example, a pulse width modulator, and in that case, the duty cycle (pulse width) of a pulse signal Sp changes according to the output VERR of the error amplifier 110B. The pulse modulator 122 may be a pulse frequency modulator or may be other modulators. The pulse modulator 122 may be in a voltage mode or may be in a peak current mode or an average current mode.
The zero controller 130B controls the gain g2 of the second amplifier AMP2 according to the output current IOUT of the DC/DC converter 100B. The detection method of the output current IOUT is not particularly limited to any kind. For example, the output current IOUT may be detected according to the coil current flowing through the inductor L11. The output current IOUT may be detected according to the current flowing through the high side transistor MH. The output current IOUT may be detected according to the current flowing through the low side transistor ML. The controller IC 300B in general includes hardware (current detection circuit) that detects at least one of the coil current, the current of the high side transistor MH, and the current of the low side transistor ML. Hence, the zero controller 130B may control the error amplifier 110B according to the amount of current detected by the hardware described above.
R represents an impedance of the load 202, and C represents a capacitance of the output capacitor C11. That is, the DC/DC converter 100B also has a pole ωp corresponding to the impedance R of the load 202, as in the linear regulator.
According to the controller IC 300B illustrated in
The configuration of the error amplifier 110B and the zero controller 130B in the second embodiment can be similar to the configuration of the error amplifier 110A and the zero controller 130A described in the first embodiment.
The type of electronic device 700 is not limited to the battery-powered device. The electronic device 700 may be an in-vehicle device, may be OA equipment such as a facsimile, or may be industrial equipment.
The embodiments are illustrative, and those skilled in the art will understand that there can be various modifications for the combinations of the constituent elements and the processes of the embodiments. The modifications will be described.
In
Although the gain g2 of the second amplifier AMP2 is successively changed according to the output current IOUT in the embodiments, the configuration is not limited to this. The gain g2 of the second amplifier AMP2 may be discretely changed, and most simply, the gain g2 of the second amplifier AMP2 may be changed in two stages. In the case of discretely changing the gain g2 of the second amplifier AMP2, the bias current IBIAS generated by the bias current source CS21 illustrated in
Although the buck converter is described as an example of the switching regulator in relation to the second embodiment, the switching regulator is not limited to this, and the present technology can also be applied to a boost converter, a buck-boost converter, and other converters.
The embodiments are illustrative, and those skilled in the art will understand that there can be various modifications for the combinations of the constituent elements and the processes of the embodiments and that the modifications can be included in the present disclosure and the scope of the present technology.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-118077 | Jul 2021 | JP | national |
