Patent Application
20240310863
This application claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2023-042572, filed on Mar. 17, 2023. The disclosure of Japanese Patent Application No. 2023-042572, including the specification, drawings and abstract is incorporated herein by reference in its entirety.
The present invention relates to a regulator circuit, for example, a capless regulator circuit that can achieve low power consumption while accepting a wide range of input voltages.
In recent years, there has been a demand for reduction in the number of components and miniaturization in electronic circuits, as well as a reduction in capacitors for improved reliability. Accordingly, the regulator circuit mounted on electronic circuits are required to be capless (capacitor-less). Furthermore, in the regulator circuit, there is a demand for low power consumption and the ability to accept a wide range of input voltages as a circuit that supplies power voltage to the area where circuits that need to operate even in deep standby are arranged, namely, the AON (Always ON) area.
There are disclosed techniques related to the regulator circuit below.
However, there has been a problem that the regulator circuit of the related technology cannot simultaneously achieve capless, acceptance of a wide range of input voltages, and low power consumption. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.
The regulator circuit according to this disclosure includes a power transistor that controls the supply of current to an external output terminal connected to a load, a monitor transistor provided between the external output terminal and a reference voltage terminal to which a reference voltage is supplied and through which a first current flows according to the voltage of the external output terminal, a first constant current source provided in series with the monitor transistor and generating a first voltage according to the difference between the first current and a first constant current, and a cascode circuit that generates a second voltage by amplifying the first voltage and supplies it to the gate of the power transistor.
The present disclosure can provide a capless regulator circuit that can achieve low power consumption while accepting a wide range of input voltages.
Hereinafter, the embodiment will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiment should not be narrowly interpreted based on the description of these drawings. Also, the same elements are given the same symbols, and redundant descriptions are omitted.
In the following embodiments, for convenience when necessary, the description is divided into multiple sections or embodiments. However, unless specifically stated, they are not unrelated to each other, and one is related to the other as a part or all of a modified example, application example, detailed explanation, supplementary explanation, etc. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless specifically stated and obviously limited to a specific number in principle, it is not limited to that specific number, and may be more or less than the specific number.
Furthermore, in the following embodiments, the constituent elements (including the operation steps and the like) are not necessarily essential except in the case where they are specifically specified and the case where they are considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of components and the like, it is assumed that the shapes and the like are substantially approximate to or similar to the shapes and the like, except for the case in which they are specifically specified and the case in which they are considered to be obvious in principle, and the like. The same applies to the above-mentioned numbers and the like, including the number, the numerical value, the amount, the range, and the like.
Before describing the regulator circuit according to the present embodiment, the regulator circuit that the present inventors have preliminarily studied will be described.
As shown in
The power transistor Mp is a P-channel MOS transistor and controls the supply of current from an input terminal (hereinafter referred to as input terminal VCC) supplied with an input voltage VCC from the outside to an output terminal OUT according to the voltage Vgp supplied to the gate. For example, in the power transistor Mp, the source is connected to the input terminal VCC, the drain is connected to the output terminal OUT, and the voltage Vgp is supplied to the gate.
The monitor transistor Mc is a P-channel MOS transistor and flows a current IMc corresponding to the voltage VDD (i.e., the voltage VDD supplied to the load) of the output terminal OUT between the source and the drain. For example, in the monitor transistor Mc, the source is connected to the output terminal OUT, the drain is connected to the input terminal (node N11) of the constant current source Ibias1, and the control voltage Vctrl is supplied to the gate.
The amplifier A1 amplifies the potential difference between the voltage VDD of the output terminal OUT and the reference voltage VREF, and outputs it as the control voltage Vctrl. Therefore, the control voltage Vctrl can be referred to as the feedback voltage of the output voltage VOUT. The output voltage VDD is maintained at the value of the reference voltage VREF by the amplifier A1 and the monitor transistor Mc.
The constant current source Ibias1 is provided between the drain (node N11) of the monitor transistor Mc and a reference voltage terminal (hereinafter referred to as reference voltage terminal VSS) supplied with the reference voltage VSS, and flows a first constant current (hereinafter referred to as constant current Ibias1) between node N11 and the reference voltage terminal VSS. Therefore, at node N11, a voltage Vgp corresponding to the difference between the current IMc flowing between the source and the drain of the monitor transistor Mc and the constant current Ibias1 flowing in the constant current source Ibias1 is generated. This voltage Vgp is supplied to the gate of the power transistor Mp.
Referring to
However, referring to
Therefore, the inventors have considered the regulator circuit 6 next. This will be explained using
As shown in
The transistor Mb1 is an N-channel MOS transistor. For example, in the transistor Mb1, the source is connected to the drain (node N11) of the monitor transistor Mc, the drain is connected to the output terminal (node N12) of the constant current source Ibias2, and a predetermined voltage Vb is supplied to the gate.
The constant current source Ibias2 is provided between the input terminal VCC and the drain (node N12) of the transistor Mb1 and flows a second constant current (hereinafter referred to as constant current Ibias2) between the input terminal VCC and node N12. Therefore, at node N12, a voltage Vgp is generated according to the constant current Ibias2 flowing through the constant current source Ibias2 and the resistance value of the transistor Mb1.
In other words, the constant current source Ibias2 and the transistor Mb1 amplify the voltage Vgn of node N11 and output it as voltage Vgp. This voltage Vgp is supplied to the gate of the power transistor Mp.
In this way, the regulator circuit 6 prevents the increase in the gate voltage Vgp of the power transistor Mp due to the increase in the input voltage VCC from being transmitted to the drain of the monitor transistor Mc by providing the transistor Mb1 between the gate of the power transistor Mp and the drain of the monitor transistor Mc. As a result, the decrease in the source-drain voltage of the monitor transistor Mc is suppressed, so the monitor transistor Mc can operate in the saturation region. In other words, the regulator circuit 6 can accept a wide range of input voltages VCC.
However, as shown in
The inventors also considered the regulator circuit 7. This will be explained using
As shown in
The transistor Ms is a P-channel MOS transistor that outputs a source voltage according to the voltage Vgpc of node N11 supplied to the gate. The transistor Ms is a so-called source follower. For example, in the transistor Ms, the source is connected to the output terminal (node N12) of the constant current source Ibias2, the drain is connected to the reference voltage terminal VSS, and the voltage Vgpc of node N11 is supplied to the gate.
The constant current source Ibias2 is provided between the input terminal VCC and the source (node N12) of the transistor Ms and flows a second constant current (hereinafter referred to as constant current Ibias2) between the input terminal VCC and node N12. Therefore, a voltage Vgp is generated at node N12 according to the constant current Ibias2 flowing through the constant current source Ibias2 and the resistance value of the transistor Ms.
In other words, the constant current source Ibias2 and the transistor Ms amplify the voltage Vgpc of node N11 and output it as voltage Vgp. This voltage Vgp is supplied to the gate of the power transistor Mp.
Thus, by providing the transistor Ms, which forms a source follower between the gate of the power transistor Mp and the drain of the monitor transistor Mc, the regulator circuit 7 can easily secure the bias point of the monitor transistor Mc and suppress the increase of the current Ibias1 flowing through the constant current source Ibias1.
However, referring to
Therefore, a capless (capacitor-less) regulator circuit 1 that can accept a wide range of input voltages while achieving low power consumption has been found.
In recent years, the semiconductor device 100 is required to reduce the number of components and miniaturize, and to reduce capacitors for improving reliability. Accordingly, the regulator circuit 1 mounted on the semiconductor device 100 is required to be capless (capacitor-less). Furthermore, the regulator circuit 1 is required to be capable of accepting a wide range of input voltages as a circuit for supplying the power supply voltage VDD to the circuit arrangement area 102, with low power consumption.
As shown in
The power transistor Mp is a P-channel MOS transistor and controls the supply of current from an input terminal (hereinafter referred to as input terminal VCC) supplied with an input voltage VCC from the outside to an output terminal OUT according to a voltage (second voltage) Vgp supplied to the gate. For example, in the power transistor Mp, the source is connected to the input terminal VCC, the drain is connected to the output terminal OUT, and the voltage Vgp is supplied to the gate.
The monitor transistor Mc is a P-channel MOS transistor and flows a current IMc corresponding to the voltage VDD (i.e., the voltage VDD supplied to the load) of the output terminal OUT between the source and drain. For example, in the monitor transistor Mc, the source is connected to the output terminal OUT, the drain is connected to the input terminal (node N11) of the constant current source Ibias1, and the control voltage Vctrl is supplied to the gate.
The amplifier A1 amplifies the potential difference between the voltage VDD of the output terminal OUT and the reference voltage VREF, and outputs it as the control voltage Vctrl. Therefore, the control voltage Vctrl can be referred to as the feedback voltage of the output voltage VOUT. The output voltage VDD is maintained at the value of the reference voltage VREF by the amplifier A1 and the monitor transistor Mc.
The constant current source Ibias1 is provided between the drain (node N11) of the monitor transistor Mc and a reference voltage terminal (hereinafter referred to as reference voltage terminal VSS) supplied with the reference voltage VSS, and flows a first constant current (hereinafter referred to as constant current Ibias1) between node N11 and the reference voltage terminal VSS. Therefore, a voltage (first voltage) Vgpc corresponding to the difference between the current IMc flowing between the source and drain of the monitor transistor Mc and the constant current Ibias1 flowing in the constant current source Ibias1 is generated at node N11.
The transistor Ms is a P-channel MOS transistor, and outputs a source voltage corresponding to the voltage Vgpc supplied to the gate. The transistor Ms is a so-called source follower. For example, in the transistor Ms, the source is connected to the source of the transistor Mb1, the drain is connected to the reference voltage terminal VSS, and the voltage Vgpc is supplied to the gate.
The transistor Mb1 is an N-channel MOS transistor and is connected in series with the transistor Ms. For example, in the transistor Mb1, the source is connected to the source of the transistor Ms, the drain is connected to the output terminal (node N12) of the constant current source Ibias2, and a predetermined voltage Vb is supplied to the gate.
The constant current source Ibias2 is provided between the input terminal VCC and the drain (node N12) of the transistor Mb1 and flows a second constant current (hereinafter referred to as constant current Ibias2) between the input terminal VCC and node N12. Therefore, a voltage (second voltage) Vgp corresponding to the constant current Ibias2 flowing in the constant current source Ibias2 and the respective resistance values of the transistors Ms and Mb1 is generated at node N12.
In the regulator circuit 1, when the load current Iload increases rapidly and the output voltage VDD drops (decreases rapidly), the current IMc flowing between the source and drain of the monitor transistor Mc decreases. As a result, the amount of charge pulled from the gate of the transistor Ms increases, causing the gate voltage (voltage of node N11) Vgpc of the transistor Ms to drop. This in turn increases the current flowing between the source and drain of the transistor Ms, causing the gate voltage (voltage of node N12) Vgp of the power transistor Mp to drop. As a result, the current flowing between the source and drain of the power transistor Mp increases, suppressing the drop in the output voltage VDD.
Here, the regulator circuit 1 prevents the increase in the gate voltage Vgp of the power transistor Mp due to the rise in the input voltage VCC from being transmitted to the drain of the monitor transistor Mc by providing a transistor Mb1 between the gate of the power transistor Mp and the drain of the monitor transistor Mc. This suppresses the drop in the voltage between the source and drain of the monitor transistor Mc, allowing the monitor transistor Mc to operate in the saturation region. In other words, the regulator circuit 1 can accept a wide range of input voltages VCC.
Furthermore, the regulator circuit 1 facilitates the bias point assurance of the monitor transistor Mc and prevents the current of the constant current source Ibias2 from flowing into the constant current source Ibias1 by providing a transistor Ms, which forms a source follower, between the gate of the power transistor Mp and the drain of the monitor transistor Mc. In other words, it can suppress the increase in the current Ibias1 flowing into the constant current source Ibias1.
The transistor Ms preferably has a gate oxide film thinner than the gate oxide film of the power transistor Mp. For example, the transistor Ms preferably has the same gate oxide film as the transistor used in the circuit (logic circuit) arranged in the circuit arrangement area 102 shown in
The monitor transistor Mc may also have a gate oxide film thinner than the gate oxide film of the power transistor Mp, similar to the transistor Ms. This allows the transistors Ms, Mb1 to be formed using the same mask as the transistor used in the circuit (logic circuit) arranged in the circuit arrangement area 102 shown in
Thus, the capless regulator circuit 1 according to the present embodiment can accept a wide range of input voltages while achieving low power consumption.
Regulator circuit 1a can achieve effects equivalent to those of regulator circuit 1. Furthermore, by using the resistor element Rs, regulator circuit 1a can reduce the impedance of the gate (node N12) of the power transistor Mp and shift the pole to the high frequency side. As a result, regulator circuit 1a can further improve the stability of the output voltage VDD.
Regulator circuit 1b can achieve effects equivalent to those of regulator circuit 1a. Furthermore, by using the transistor Mb2, which is a depletion-type N-channel MOS transistor, regulator circuit 1b can lower the threshold voltage than transistor Mb1, thereby lowering the lower limit of the acceptable input voltage VCC.
In this example, the case where the transistor Mb1 of regulator circuit 1a is replaced with transistor Mb2 is described, but this is not limited to this. Of course, the transistor Mb1 of regulator circuit 1 may be replaced with transistor Mb2.
Regulator circuit 1c can achieve effects equivalent to those of regulator circuit 1b. Furthermore, by providing the capacitive element C1 between the nodes that are in phase in the feedback path from the output terminal OUT to the gate of the power transistor Mp via transistors Mc, Ms, and Mb2, regulator circuit 1c can form a zero point and further improve the stability of the output voltage VDD.
In this example, the case where the capacitive element C1 is added to regulator circuit 1b is described, but this is not limited to this. Of course, the capacitive element C1 may be added to any of regulator circuits 1 to 1a.
Regulator circuit 1d can achieve an effect equivalent to that of regulator circuit 1b. Furthermore, by providing the capacitive element C2 between the nodes that are in phase in the feedback path from the output terminal OUT to the gate of the power transistor Mp via transistors Mc, Ms, Mb2, regulator circuit 1d can form a zero point and further improve the stability of the output voltage VDD.
In this example, although the case where the capacitive element C2 is added to the regulator circuit 1b is described, it is not limited to this. Of course, the capacitive element C2 may be added to any of regulator circuits 1 to 1a.
Regulator circuit 1e can achieve an effect equivalent to that of regulator circuit 1b. Furthermore, by providing the capacitive elements C1 and C2 between the nodes that are in phase in the feedback path from the output terminal OUT to the gate of the power transistor Mp via transistors Mc, Ms, Mb2, regulator circuit 1d can form a zero point and further improve the stability of the output voltage VDD.
In this example, although the case where the capacitive elements C1 and C2 are added to the regulator circuit 1b is described, it is not limited to this. Of course, the capacitive elements C1 and C2 may be added to any of regulator circuits 1 to 1a.
Amplifier A2 amplifies the potential difference between the voltage divided by the output voltage VDD using resistive elements R1 and R2 and the reference voltage VREF, and outputs it as control voltage Vctrl. Here, amplifier A2 is driven by the output voltage VDD and is composed of multiple transistors with a gate oxide film thickness thinner than that of the power transistor (i.e., transistors used in logic circuits). The other components of regulator circuit 1f are the same as those of regulator circuit 1b, so their description is omitted.
Regulator circuit 1f can achieve an effect equivalent to that of regulator circuit 1b. Furthermore, by using amplifier A2 driven by the output voltage VDD, regulator circuit 1f can reduce the impedance of the regulator output, thereby further improving the stability of the output voltage VDD.
In this example, although the description has been made on the case where the amplifier A1 of the regulator circuit 1b is replaced with the amplifier A2, it is not limited thereto. Naturally, the amplifier A1 of any of the regulator circuits 1, 1a, 1c, 1d, 1e may be replaced with the amplifier A2.
The regulator circuit 1g can achieve an effect equivalent to that of the regulator circuit 1f. Furthermore, the regulator circuit 1g can form a zero point between the amplifier A2, the resistive element Resr, and the on-chip capacitance, and can further improve the stability of the output voltage VDD.
As described above, the capless regulator circuit according to the above embodiment can accept a wide range of input voltages while achieving low power consumption.
Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment already described, and it is needless to say that various modifications can be made without departing from the gist thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-042572 | Mar 2023 | JP | national |
