Patent Grant
7439798
1. Field of the Invention
The present invention relates to a regulator circuit, and relates particularly to a regulator circuit that can quickly recover from the halted state to the operating state.
2. Description of the Related Art
In order to generate a desired internal voltage, a regulator circuit is mounted in a semiconductor integrated circuit. The regulator circuit is used, for example, when a power voltage required for the internal operation of a semiconductor integrated circuit is to be generated based on an externally input power voltage. Also, for a semiconductor memory device, the regulator circuit is employed when a predetermined voltage used for a reading or a writing operation is to be generated based on a voltage output by a charge pump circuit.
Currently, a demand exists for low power consumption semiconductor integrated circuits that can be mounted in portable devices, such as cellular phones. In use, when such a semiconductor integrated circuit enters a standby state, a regulator circuit mounted thereon should be halted to limit the consumption of power. And later, when the semiconductor integrated circuit recovers from the standby state to the active state, the regulator circuit must be able to recover quickly and supply predetermined voltages.
The detection circuit 11 is a series circuit that includes resistors R0 and R1, which are connected between the output voltage VOUT terminal and the ground voltage terminal, and an N-channel transistor N0. The feedback voltage VFB is extracted at the juncture of the resistors R0 and R1, and the gate of the N-channel transistor N0 is connected to a contact for a control signal ENREG.
The feedback voltage VFB is applied to the non-inverted input terminal of the operational amplification circuit 12 and the reference voltage VREF is applied to the inversion input terminal, and the operational amplification circuit 12 is driven by a power source HV. Further, the control signal ENREG is transmitted to the operational amplification circuit 12.
The output circuit 13 is a P-channel transistor P0, and the gate is connected to the output terminal VAOUT of the operational amplification circuit 12, the source is connected to the power source HV, and the drain is connected to the output terminal VOUT. In accordance with the output voltage VAOUT of the operational amplification circuit 12, a current is supplied to the output terminal VOUT.
The control signal ENREG is a control signal for controlling the starting and the halting of the operation of the regulator circuit 100. When the control signal ENREG is at level H, the N-channel transistor N0 in the detection circuit 11 is set to the ON state, the operational amplification circuit 12 is activated, and the regulator circuit 100 is set to the operating state. When the control signal ENREG is at level L, the N-channel transistor N0 in the detection circuit 11 is set to the OFF state, the operational amplification circuit 12 is inactivated, and the regulator circuit 100 is halted. At this time, the power consumed by the regulator circuit 100 drops to zero.
A decoupling capacitor 30 and a load circuit 31 are connected to the output terminal VOUT of the regulator circuit 100. The decoupling capacitor 30 is additionally provided in order to suppress the fluctuation of the output voltage VOUT. The load circuit 31 is a destination to which the output voltage is supplied, and an actual load is represented as a model by using a current source IL and a switch SW.
Hereinafter, assume this is a case wherein the reference voltage VREF=1.25 V, the power voltage HV=5.4 V and the output voltage VOUT=4.6 V. These voltage values are employed for a case wherein the regulator circuit generates a voltage of 4.6 V to be applied to a word line during a reading operation for a flash memory. The power voltage HV=5.4 V is generated by raising the internal power voltage of 1.8 V using the charge pump circuit.
When the control signal ENREG is at level L, the regulator circuit 100 is in the standby state (the halted state), and the current consumed by the detection circuit 11 and the operational amplification circuit 12 is zero. When the load circuit 31 is to consume current while the regulator circuit is in the standby state, the control signal ENREG goes to level H and the regulator circuit recovers from the standby state to the active state and begins to supply a current to the load circuit 31.
As shown in
When at this time any current is not consumed by the load circuit 31, the control signal ENREG goes to level L and the regulator circuit is shifted to the standby state. At this time, the current consumed by the detection circuit 11 and the operational amplification circuit 12 is zero. Further, the power voltage HV is output by the output terminal VAOUT of the operational amplification circuit 12, and thus, the P-channel transistor P0 in the output circuit 13 is rendered OFF and the output terminal VOUT is set to a high impedance state.
As a result, the capacitance C of the decoupling capacitor 30 maintains the output voltage VOUT in the standby state at the voltage 4.6 V in the operating state. Since the N-channel transistor N0 in the detection circuit 11 is in the OFF state, the feedback voltage VFB is set so it is near the output voltage 4.6 V. When the load circuit 31 consumes current while the regulator circuit is in the standby state, the control signal ENREG goes to level H, and the regulator circuit recovers from the standby state to the active state and begins to supply a current to the load circuit 31 (see, for example, JP-A-2002-312043 and JP-A-2000-331479).
However, the conventional regulator circuit cannot quickly recover from the standby state to the active state. In the standby state, as shown in
Since the load circuit 31 continuously consumes current during a period lasting until the regulator circuit is shifted to the stable operation state and begins to supply a current, there is a large voltage drop VD2 in the output voltage VOUT.
To prevent this voltage drop VD2, an increase in the value of the capacitance C of the decoupling capacitor 30 is considered. However, in this case, the chip area would be increased because a larger decoupling capacitor would be employed, and accordingly, the cost of the semiconductor integrated circuit would be increased.
To resolve these shortcomings, one objective of the present invention to provide a regulator circuit that can quickly recover from the standby state to the active state, without requiring an increase in the chip area.
To achieve this objective, a regulator circuit according to the present invention comprises:
a detection circuit, for outputting a feedback voltage in accordance with an output voltage;
a reference voltage input section;
a feedback voltage input section;
an operational amplification circuit, for comparing a reference voltage and the feedback voltage and outputting a voltage as a comparison result;
an output circuit, for supplying an output voltage in accordance with the output of the operational amplification circuit;
a connection/disconnection circuit, for connecting or disconnecting an output terminal of the detection circuit and the feedback voltage input section; and
a voltage setup circuit, for setting for the feedback voltage input section a predetermined voltage.
It is preferable, when the regulator circuit of the present invention is activated, that the detection circuit and the operational amplification circuit be activated and the output terminal of the detection circuit and the feedback voltage input section be connected by the connection/disconnection circuit, and that the voltage setup circuit be set to the inactive state.
Further, it is preferable, when the regulator circuit of the present invention is halted, that the detection circuit and the operational amplification circuit stop the consumption of current and halt their operations, that the output terminal of the detection circuit and the feedback voltage input section be disconnected by the connection/disconnection circuit, and that for the feedback voltage input section a predetermined voltage be set by the voltage setup circuit.
It is also preferable that the activation and the halting of the regulator circuit of the invention be controlled in response to a control signal.
Furthermore, it is preferable, for the regulator circuit of the invention, that the connection/disconnection circuit include a first P-channel transistor for connecting or disconnecting the output terminal of the detection circuit and the feedback voltage input section.
Moreover, it is preferable, for the regulator circuit of the invention, that the voltage setup circuit can be set to a voltage near the reference voltage.
It is also preferable, for the regulator circuit of the invention, that the voltage setup circuit can be set to an internal power voltage used inside a semiconductor integrated circuit.
Further, it is preferable, for the regulator circuit of the invention, that the voltage setup circuit include a second P-channel transistor for setting the internal power voltage for the feedback voltage input section.
Furthermore, it is preferable, for the regulator circuit of the invention, that the voltage setup circuit can be set to the reference voltage.
Moreover, it is preferable, for the regulator circuit of the invention, that the voltage setup circuit include a third P-channel transistor for setting the reference voltage for the feedback voltage input section.
It is also preferable, for the regulator circuit of the invention, that the voltage setup circuit have a series-connection structure including at least one N-channel transistor, the gate and the drain of which are connected in common between the feedback voltage input section and a ground voltage terminal.
Further, it is preferable, for the regulator circuit of the invention, that after a predetermined time has elapsed following the shifting of the regulator circuit was shifted from a halted state to an operating state, the connection/disconnection circuit connects the output terminal of the detection circuit to the feedback voltage input section.
As described above, according to the regulator circuit of the invention, in the standby state (the halted state), the detection circuit and the feedback voltage input section can be disconnected, and a predetermined voltage can be set for the feedback voltage input section. Since in the standby state a voltage set for the feedback voltage input section is near the reference voltage, when the standby state is returned to the active state, the potential for the feedback voltage input section is changed, within a short period of time, to the reference voltage, which that is the a potential for a stable operation. Therefore, the quick recovery of the regulator circuit can be achieved.
Furthermore, since the internal power voltage used inside a semiconductor integrated circuit is employed as a voltage to be set for the feedback voltage input section in the standby state, a voltage near the reference voltage can be designated for the feedback voltage input section in the standby state, without the generation of a setup voltage for the feedback voltage input section being required. Thus, when in a short period of time the regulator circuit is recovered from the standby state to the active state, the potential of the feedback voltage input section can be set to the reference voltage, that is the potential for a stable operation. In this manner, the quick recovery of the regulator circuit can be achieved.
When the standby state and the active state are to be frequency shifted, the voltage setup should be quickly performed for the feedback voltage input section. There is no problem in performing this setup, because the voltage to be set in the feedback voltage input section is the internal power voltage.
Further, since the reference voltage is employed as a voltage to be set for the feedback voltage input section in the standby state, a new voltage to be set for the feedback voltage input section need not be generated. According to this arrangement, when the regulator circuit recovers from the standby state to the active state, the potential of the feedback voltage input section is set to the reference voltage, so that a quick recovery of the regulator circuit can be achieved.
In addition, a series-connection structure including at least one N-channel transistor, the gate and the drain of which are connected in common between the feedback voltage input section and the ground voltage terminal, is employed as means for setting a predetermined voltage for the feedback voltage input section in the standby state. According to this arrangement, the voltage set for the feedback voltage input section in the standby state is determined to be integer times a threshold voltage Vt of the N-channel transistor. When a transistor having an optimal threshold voltage is selected, a voltage, near the reference voltage, that does not depend on the power voltage can be set. With this arrangement, when the standby state is recovered to the active state, the potential for the feedback voltage input section is set, in a short period of time, to the reference voltage that is the potential for a stable operation, so that the quick recovery of the regulator circuit can be achieved.
After a predetermined period of time has elapsed following the shifting of the regulator circuit from the halted state to the operating state, the connection/disconnection circuit connects the output terminal of the detection circuit to the feedback voltage input section. According to this arrangement, when the active state is to be recovered from the standby state, the output terminal of the detection circuit and the feedback voltage input section can be connected after the output voltage of the detection circuit has been stabilized. Therefore, when the standby state is shifted to the active state, the feedback voltage input section is more quickly set to the reference voltage, which is the potential for a stable operation. Therefore, a quicker regulator circuit recovery can be achieved.
The preferred embodiments of the present invention will now be described in detail while referring to the drawings.
A regulator circuit 110 according to the embodiments of the invention includes: a connection/disconnection circuit 21, for connecting or disconnecting the output terminal of a detection circuit 11 and a feedback input section VFB; and a voltage setup circuit 22, for setting a predetermined voltage for the feedback input section VFB.
When the regulator circuit 110 is in the operating state, the connection/disconnection circuit 21 connects the output terminal of the detection circuit 11 to the feedback input section VFB, and the voltage setup circuit 22 is set to the inactive state.
When the regulator circuit 110 is in the halted state, the detection circuit 11 and an operational amplification circuit 12 halt current consumption and stop the operations, the connection/disconnection circuit 21 disconnects the output terminal of the detection circuit 11 from the feedback input section VFB, and the voltage setup circuit 22 sets a predetermined voltage for the feedback input section VFB.
More detailed examples for the invention will be explained while referring to the drawings.
A regulator circuit 120 according to this embodiment includes: a connection/disconnection circuit 21, for connecting or disconnecting the output terminal of a detection circuit 11 and a feedback input section VFB; and a voltage setup circuit 22, for setting a predetermined voltage for a feedback input section VFB.
The connection/disconnection circuit 21 is constituted by a P-channel transistor P1, and the gate is attached to the output terminal of a level shifter circuit LS1. Based on a control signal ENREG, the P-channel transistor P1 either connects the detection circuit 11 to the feedback input section VFB, or disconnects the detection circuit 11 from the feedback input section VFB.
The level shifter LS1 shifts the voltage level of the control signal ENREG to a power voltage level HV, and the logic for the shifting is inverted logic (inverter).
The voltage setup circuit 22 is constituted by a P-channel transistor P2. The source of the P-channel transistor P2 is connected to the 1.8 V internal power source used by a semiconductor integrated circuit, the drain is connected to the feedback input section VFB, and the gate is connected to a contact for the control signal ENREG. Based on the control signal ENREG, the P-channel transistor P2 sets the 1.8 V internal power voltage for the feedback input section VFB.
The amplification circuit 41 includes: P-channel transistors PA1 and PA2, which form a current mirror circuit, a differential pair of N-channel transistors NA1 and NA2, and an N-channel transistor NA0, which is a constant current source.
The gate and the drain of the P-channel transistor PA1 and the gate of the P-channel transistor PA2 are connected in common to the node N0, and the sources of the P-channel transistors PA1 and PA2 are connected to the power source HV.
The drain of the P-channel transistor PA1 is connected to the drain of the N-channel transistor NA1, and the drain of the P-channel transistor PA2 and the drain of the N-channel transistor NA2 are connected in common to the output terminal VAOUT.
The feedback voltage VFB is applied to the gate of the N-channel transistor NA1, and the reference voltage VREF is applied to the gate of the N-channel transistor NA2. Further, the sources of the N-channel transistors NA1 and NA2 are connected in common, and the N-channel transistor NA0 is connected between this junction and the ground voltage terminal. A bias voltage VBIAS is applied to the gate of the N-channel transistor NA0 by the bias voltage generation circuit 42.
Based on the control signal ENREG, the bias voltage generation circuit 42 generates the bias voltage VBIAS. When the control signal ENREG is at level H, i.e., when the regulator circuit 120 is in the operating state, the bias voltage generation circuit 42 generates the bias voltage VBIAS, and the differential amplification circuit 41 is rendered active and compares the feedback voltage VFB with the reference voltage VREF. At this time, the bias voltage generation circuit 42 consumes a current of several tens of micro amperages to generate the bias voltage VBIAS.
When the control signal ENREG is at level L, i.e., when the regulator circuit 120 is in the halted state, the bias voltage generation circuit 42 is halted, and the ground voltage level is set for the output voltage VBIAS. At this time, the current consumed by the bias voltage generation circuit 42 is zero. Similarly, the current consumed by the differential amplification circuit 41 is also zero, and the regulator circuit 120 is completely halted.
The differential amplification circuit halt circuit 43 includes P-channel transistors PA3 and PA4 and a level shifter circuit LS2. The gates of the P-channel transistors PA3 and PA4 are connected to the output terminal of the level shifter circuit LS2, and the source is connected to the power source HV. Further, the drain of the P-channel transistor PA3 is connected to the node N0, and the drain of the P-channel transistor P4 is connected to the output terminal VAOUT.
The level shifter circuit LS2 shifts the voltage level of the control signal ENREG to the power voltage level HV, and the output voltage is applied to the gates of the P-channel transistors PA3 and PA4. When the control signal ENREG is at level H, i.e., when the regulator circuit 120 is in the operating state, the P-channel transistors PA3 and PA4 are rendered off and do not affect the operation of the differential amplification circuit 41. When the control signal ENREG is at level L, i.e., when the regulator circuit 120 is in the halted state, the P-channel transistors PA3 and PA4 are rendered on, and the power voltage HV is set for the node N0 and the output terminal VAOUT of the differential amplification circuit 41.
Various operations of the regulator circuit 120, according to the first embodiment, arranged as in
When the control signal ENREG is at level L, the regulator circuit 120 is in the standby state (the halted state), and the current consumed by the detection circuit 11 and the operational amplification circuit 12 is zero. When the load circuit 31 is to consume a current while the regulator circuit 120 is in the standby state, the control signal ENREG goes to level H, and the regulator circuit 120 recovers from the standby state to the active state and begins to supply a current to the load circuit 31.
As shown in
When no current is consumed by the load circuit 31, the control signal ENREG goes to level L, and the regulator circuit 120 is shifted to the standby state. At this time, the current consumed by the detection circuit 11 and the operational amplification circuit 12 is zero. Further, the power voltage HV is output at the output terminal VAOUT by the operational amplification circuit 12, and as a result, the P-channel transistor P0 of the output circuit 13 is rendered off and the output terminal VOUT is set to the high impedance state. In the standby state, the output voltage VOUT, 4.6 V, used for the operation is maintained by a capacitance Cat a decoupling capacitor 30.
The P-channel transistor P1 of the connection/disconnection circuit 21 is rendered off by applying to the gate the power voltage HV from the level shifter circuit LS1, and the output terminal of the detection circuit 11 is disconnected from the feedback input section VFB.
Furthermore, the P-channel transistor P2 of the voltage setup circuit 22 is rendered on by applying the ground voltage (the control signal ENREG at level L) to the gate, and the internal power voltage of 1.8 V is set for the feedback input section VFB.
According to the conventional regulator circuit, as previously explained while referring to
When the load circuit 31 consumes current while the regulator circuit 120 is in the standby state, the control signal ENREG goes to level H, and the regulator circuit 120 recovers from the standby state to the active state and begins to supply current to the load circuit 31.
When the regulator circuit 120 has been shifted to the active state, the N-channel transistor NO of the detection circuit 11 is rendered on, the operational amplification circuit 12 is rendered active, and the regulator circuit 120 begins operation. Furthermore, the P-channel transistor P1 of the connection/disconnection circuit 21 is rendered on by applying to the gate the ground voltage from the level shifter circuit LS1, and the output terminal of the detection circuit 11 is connected to the feedback input section VFB.
In addition, the P-channel transistor P2 of the voltage setup circuit 22 is rendered off by applying the internal power voltage (the control signal ENREG at level H) to the gate, and the setting of the internal power voltage 1.8 V for the feedback input section VFB is canceled.
Then, the feedback input section VFB is shifted to the reference voltage VREF (1.25 V), which is the stable voltage for the operation of the regulator circuit 120. At this time, since the voltage of the feedback input section VFB in the standby state is the internal 1.8 V power voltage, a time T required before the regulator circuit 120 is shifted to the stable operating state is reduced, when compared with the time required for the conventional regulator circuit.
Therefore, the regulator circuit 120 can quickly recover, and a drop VD3 in the output voltage VOUT is sharply reduced, when compared with the conventional regulator circuit. Therefore, the capacitance C of the decoupling capacitor 30 need not be increased in order to prevent the drop in the output voltage VOUT, and the need to increase the chip area can be eliminated.
Moreover, when the standby state and the active state are switched frequently, the voltage for the feedback input section VFB can be quickly set, because the internal power voltage is employed and is set for the feedback input section VFB. Thus, rapid switching between the standby state and the active state of the regulator circuit is enabled.
A difference between a regulator circuit 130 of this embodiment and the regulator circuit of the first embodiment in
In
The regulator circuit 130 in the second embodiment is characterized by being set at the reference voltage VREF by the P-channel transistor P2 when the regulator circuit 130 is in the standby state. With this arrangement, in the standby state, the voltage of the feedback input section VFB can be set for the reference voltage VREF, which is a voltage for a stable operation in the active state. Therefore, the regulator circuit 130 can quickly recover from the standby state to the active state.
However, when the voltage setup of the feedback input section VFB is performed frequently, noise may be injected into the reference voltage VRE, because the reference voltage VREF is employed for the voltage setup. Thus, when the regulator circuit is frequently shifted between the standby state and the active state, this embodiment need be applied while referring to the shifting frequency. However, since the voltage at the feedback input section VFB in the standby state equals the reference voltage VREF, in the standby state, the regulator circuit can at least quickly recover to the active state.
A difference between a regulator circuit 140 of this embodiment and the regulator circuit 120 of the first embodiment in
In
The inverter circuit INV is an inverter circuit that receives a control signal ENREG, and the output terminal is connected to the gate of the N-channel transistor N11.
When the control signal ENREG is at level H, i.e., when the regulator circuit 140 is active, the output of the inverter circuit INV is at level L, the N-channel transistor N11 is rendered off, and the voltage setup circuit 22 does not affect the feedback input section VFB.
When the control signal ENREG is at level L, i.e., when the regulator circuit 140 is in the standby state, the output of the inverter circuit INV is at level H, the N-channel transistor N11 is rendered on, and the feedback input section VFB is grounded via the N-channel transistors N11, N21 and N22.
Therefore, assuming that the threshold voltages of the N-channel transistors N21 and N22 are defined as Vt, in the standby state the feedback input section VFB is set at a voltage 2Vt by the diode-connected N-channel transistors N21 and N21. When the threshold voltages of the N-channel transistors N21 and N22 are near 0.625 V, in the standby state the feedback input section VFB is set at a voltage 1.25 V, which has the same potential as the reference voltage VREF. Therefore, the regulator circuit 140 can quickly recover from the standby state to the active state.
The components of a regulator circuit 150 for this embodiment are the same as those for the regulator circuit 120 of the first embodiment in
In
In
After predetermined time TD has elapsed, the control signal ENREG2 goes to level H, and the connection/disconnection circuit 21 connects the output terminal of the detection circuit 11 to the feedback input section VFB, the voltage setup circuit 11 is rendered inactive, and the operational amplification circuit 12 is activated.
At this time, the detection circuit 11 is in the operating state before it is connected to the feedback input section VFB by the connection/disconnection circuit 21. Thus, the output of the detection circuit 11 is a voltage (1.25 V) for a stable operation.
Therefore, the reference voltage VREF, which is a voltage for a stable operation, is more quickly set for the feedback input section VFB. As a result, the recovery operation for shifting the regulator circuit from the standby state to the active state can be performed at high speed.
The present invention has been described by referring to the first to the fourth embodiments. The regulator circuit of the invention is not limited to these embodiments, and various modifications can be applied without departing from the subject of the invention.
The regulator circuit according to the invention is characterized by being capable of quickly recovering from the standby state to the active state, and is effective, for example, as means for generating an internal power voltage for a semiconductor integrated circuit for which low power consumption is requested, and as means for generating a voltage required for data reading and writing relative to a semiconductor memory device.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2004-333312 | Nov 2004 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5982226 | Rincon-Mora | Nov 1999 | A |
| 7046079 | Van Blerkom et al. | May 2006 | B2 |
| Number | Date | Country |
|---|---|---|
| 2000-331479 | Nov 2000 | JP |
| 2002-083494 | Mar 2002 | JP |
| 2002-312043 | Oct 2002 | JP |
| 2004157613 | Jun 2004 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20060119421 A1 | Jun 2006 | US |
