Patent Application
20250239970
The disclosure relates to a relaxation oscillator that oscillates using the on/off of a switch.
Conventionally, as one of oscillation circuits, a relaxation oscillator that generates intermittent electrical signals by controlling on/off timing of a switch is known. For example, a capacitor is charged, a comparator detects that the charging voltage thereof has reached a predetermined value, and the on/off timing of the switch is determined.
In view of this, for accurate and stable oscillation, the comparator requires high speed and high precision, which consumes large currents and requires large-scale circuits.
In addition, when the comparator detects that the charging voltage of the capacitor has reached the predetermined value, the charging current becomes smaller in the vicinity of a trigger point, and therefore, there is a problem that an operation at the trigger point is likely to be unstable.
A relaxation oscillator related to the disclosure includes: a first transistor, through which a constant current is made to flow; a first capacitor, which is charged by a current from the first transistor; a second transistor, which draws a charge of the first capacitor; a third transistor, through which a constant current is made to flow; a second capacitor, which is charged by a current from the third transistor; a fourth transistor, which draws a stored charge of the second capacitor; and a flip-flop, whose state changes from a first state to a second state when a charging voltage of the first capacitor reaches a predetermined value, and changes from the second state to the first state when a charging voltage of the second capacitor reaches a predetermined value, the flip-flop causing the second transistor to be turned off and the fourth transistor to be turned on in the first state, and causing the second transistor to be turned on and the fourth transistor to be turned off in the second state; and the relaxation oscillator outputs a signal of a predetermined frequency from the flip-flop.
According to the relaxation oscillator related to the disclosure, a constant current is used for charging, the slope of the voltage is still constant even in the vicinity of the trigger point, and therefore a stable operation can be obtained.
Hereinafter, embodiments of the disclosure will be described below with reference to the drawings. Note that, the following embodiments do not limit the scope of the disclosure, and configurations obtained by selectively combining multiple examples are also included in the disclosure.
The source of a p-channel transistor M0 is connected to a power supply Vdd, and the drain is connected to a ground GND via a resistor R0. There is a short circuit, that is a diode connected between the gate and the drain of the transistor M0. Accordingly, a constant current Iref determined by a voltage (Vdd) of the power supply Vdd and a resistance value of the resistor R0 flows through the transistor M0 and the resistor R0.
The gate of a p-channel transistor M1 is connected to the gate of the transistor M0. The source of the transistor M1 is connected to the power supply Vdd, and the drain is connected to the ground GND via a capacitor C1. Because the transistor M0 and the transistor M1 constitute a current mirror, by making the two transistors equivalent, the same current Iref as the transistor M0 flows through the transistor M1, and the capacitor C1 is charged with the current Iref. Moreover, by changing the ratio of the size of the input side transistor to the size of the output side transistor of the current mirror, the ratio of the currents flowing through the two transistors can be changed.
In addition, the drain of an n-channel transistor M2 is connected to a connection point between the drain of the transistor M1 and the capacitor C1, and the source of the transistor M2 is connected to the ground. Accordingly, the capacitor C1 is discharged when the transistor M2 is turned on.
The gate of a p-channel transistor M3 is also connected to the gate of the transistor M0. The source of the transistor M3 is connected to the power supply Vdd, and the drain is connected to the ground GND via a capacitor C2. Because the transistor M0 and the transistor M3 constitute a current mirror, the same current Iref as the transistor M1 also flows through the transistor M3, and the capacitor C2 is charged with the current Iref.
In addition, the drain of an n-channel transistor M4 is connected to a connection point between the drain of the transistor M3 and the capacitor C2, and the source of the transistor M4 is connected to the ground. Accordingly, the capacitor C2 is discharged when the transistor M4 is turned on.
The gate of a transistor M5 is connected to the drain of the transistor M1. The transistor M5 is a p-channel transistor, the source is connected to the power supply Vdd, and the drain is connected to the ground GND via a resistor R1. The transistor M5 is turned on when a difference between its gate voltage (=a charging voltage Vc1 of the capacitor C1) and a power supply voltage Vdd is greater than or equal to a predetermined value, that is, a threshold voltage Vgson, and the transistor M5 is turned off when the difference is less than or equal to the predetermined value. In other words, the transistor M5 is turned off when its gate voltage Vc1 becomes greater than or equal to Vdd−Vgson.
The gate of a transistor M6 is connected to the drain of transistor M3. The transistor M6 is a p-channel transistor, the source is connected to the power supply Vdd, and the drain is connected to the ground GND via a resistor R2. The transistor M6 is turned off when a difference between its gate voltage (=a charging voltage Vc2 of the capacitor C2) and the power supply voltage Vdd becomes less than or equal to the threshold voltage Vgson. That is, the transistor M6 is turned off when its gate voltage Vc2 becomes greater than or equal to Vdd−Vgson.
The drain of the transistor M5 is connected to a low active set terminal Sb of an RS type flip-flop FF. In addition, the drain of the transistor M6 is connected to a low active set terminal Rb of the flip-flop FF. An output terminal Q of the flip-flop FF is connected to the gate of the transistor M2, and an inverted output terminal Qb is connected to the gate of the transistor M4.
First, the state of the flip-flop FF is assumed to be “0”. In this case, the output terminal Q is at L level, the transistor M2 is off, the inverted output terminal Qb is at H level, and the transistor M4 is on. Accordingly, the capacitor C1 is charged with a constant current, and the voltage Vc1 gradually rises. On the other hand, because the transistor M4 is on, the voltage Vc2 remains at 0 V.
The voltage Vc1 of the capacitor C1 rises, and when the gate voltage of the transistor M5 becomes greater than or equal to Vdd−Vgson, the transistor M5 is turned off. Thereby, the current flowing through the resistor R1 disappears, and the voltage of a connection portion between the resistor R1 and the transistor M5 becomes 0 V. Therefore, the low active set-terminal Sb of the flip-flop FF changes from H level to L level. Thereby, the state of the flip-flop FF becomes “1”, the output terminal Q is at H level, and the inverted output terminal Qb is at L level.
Thereby, the transistor M2 is turned on and the transistor M4 is turned off. Accordingly, the capacitor C1 is discharged and the voltage Vc1 becomes 0 V. On the other hand, because the transistor M4 is turned off, the capacitor C2 is charged, and the voltage Vc2 gradually rises. Furthermore, because the transistor M2 is on, the voltage Vc1 remains at 0 V.
The voltage Vc2 of the capacitor C2 rises, and when the gate voltage of the transistor M6 becomes greater than or equal to the threshold voltage, the transistor M6 is turned off. Therefore, the low active reset terminal Rb of the flip-flop FF changes from H level to L level, the state of the flip-flop FF becomes “0”, the output terminal Q is at L level, and the inverted output terminal Qb is at H level.
Thereby, the transistor M2 is turned off and the transistor M4 is turned on. Accordingly, the capacitor C2 is discharged and the voltage Vc2 becomes 0 V. On the other hand, the capacitor C1 begins to be charged and the voltage Vc1 gradually rises. Because the transistor M4 is on, the voltage Vc2 remains at 0 V.
In this way, by charging the capacitors C1 and C2 with a constant current flowing through the transistors M1 and M3, the state of the flip-flop FF changes to “0” and “1” every predetermined duration. Accordingly, a signal of a predetermined frequency can be obtained at the output of the flip-flop FF.
If the transistors M1 and M3 have a similar configuration, and the capacitors C1 and C2 have the same capacitance, the charging of the capacitors C1 and C2 can be made equivalent, and time t1 during which the state of the flip-flop FF is “O” and time t2 during which the state of the flip-flop FF is “1” can be made the same.
Moreover, the two states of the flip-flop FF are respectively referred to as a first state and a second state. Which one of the two states is the first state or the second state is arbitrary, as long as they refer to different states of “0” or “1” respectively.
Next, the above operation is described using equations. Here, it is assumed that M0:M1:M3=1:1:1, C1=C2=C, td (operation delay time)<<t1 (½ of the output period). In addition, the charging current is set to Iref, and the threshold voltage of the transistor is set to Vgson.
First, a charge q of the capacitor is a value obtained by multiplying a capacitance C of the capacitor by its voltage V.
q=C*V
The charge q of the capacitor is a value obtained by multiplying a current I by charging time t.
I*t=q=C*V
The transistors M5 and M6 are turned off when the voltages of the capacitors C1 and C2 become greater than or equal to (Vdd−Vgson).
Accordingly,
Iref*t1=C1*(Vdd−Vgson).
Therefore,
t1=C1*(Vdd−Vgson)/Iref.
In addition, the charging current Iref is a current flowing through the resistor R0 on the downstream side of the transistor M0, and the voltage drop in the diode-connected transistor M0 is Vgson, and therefore,
Iref=(Vdd−Vgson)/R0.
Accordingly,
t1=C1*R0=C*R0.
t2 is also the same,
t2=C2*R0=C*R0=t1.
Thus, the clock timing does not depend on the power supply, and the duty ratio is 50%.
Because the relaxation oscillator according to the embodiment uses a constant current for charging, the slope of the voltage is constant at a trigger point where the transistors M5 and M6 are turned off, and a stable operation is obtained. For example, a capacitor-resistor (CR) type relaxation oscillator has a problem in the operation at the trigger point because the charging current becomes smaller in the vicinity of the trigger point, but this kind of problem does not exist in the relaxation oscillator related to the disclosure.
In addition, in the embodiment, it is sufficient to control the on/off of the transistors M5 and M6 by the charging voltage of the capacitor, so that the current consumption may be relatively small, and a high-speed operation can be realized with a simple configuration.
In addition, because switching can be performed using the charging voltage of the capacitor, which is close to the power supply voltage, it is resistant to noise and suitable for miniaturization of the capacitor.
Because the charging current of the capacitor is the current flowing through the transistors M1 and M3 and is proportional to the comparison voltage (Vdd−Vgson), and a voltage at which the charging is stopped is also (Vdd−Vgson), the time constant of the circuit operation does not depend on the power supply voltage.
That is, a p-channel transistor M8 whose gate is connected to the transistor M0 and whose source is connected to the power supply Vdd is arranged, and a current corresponding to the current Iref flowing through the transistor M0 is made to flow here. The drain of the transistor M8 is connected to the drain of an n-channel transistor M9. There is a short circuit, that is, a diode connected between the gate and the drain of the transistor M9, and the source is connected to the ground.
The gate of an n-channel transistor M10 is connected to the gate of the transistor M9, and the drain of the transistor M10 is connected to the source of the transistor M5. The transistor M9 and the transistor M10 constitute a current mirror. The transistor M5 makes a sufficient current flow in the case of on, but when the transistor M5 is on, the current flowing through the transistor M5 becomes the same current as the transistor M10, and the drain of the transistor M5, that is, the low active set terminal Sb of the flip-flop FF is at H level. On the other hand, when the transistor M5 is off, in order to make a current flow through the transistor M10, the drain of the transistor M5, that is, the low active set terminal Sb of the flip-flop FF is at L level.
In addition, although the timing is opposite, a transistor M11 operates in the same manner as the transistor M10, and the low active set terminal of the flip-flop FF is at H level when the transistor M6 is on, and is at L level when the transistor M6 is off. Moreover,
In this way, in this Variation example 1, the same operation as the example of
That is, the sources of the p-channel transistors M12 and M13 are connected to the drain of the transistor M1. The drain of the transistor M12 is connected to the capacitor C1, and the drain of the transistor M13 is connected to the capacitor C2. In addition, the gate of the transistor M12 is connected to the output terminal Q of the flip-flop FF, and the gate of the transistor M13 is connected to the inverted output terminal Qb of the flip-flop FF.
Accordingly, when the transistor M2 is off, the transistor M12 is turned on and the capacitor C1 is charged, and when the transistor M4 is off, the transistor M13 is turned on and the capacitor C2 is charged.
According to the embodiments, an oscillator, which is a relatively simple circuit, is easy to implement, and also has a small number of components, can be realized. By making the charging voltages of the capacitors C1 and C2 close to the voltage of the power supply Vdd, the transistors M5 and M6 are turned off, and therefore it is possible to make full use of the power supply voltage to oscillate, furthermore, phase noise can be reduced.
The gates and sources of the transistors M5 and M6 operate as a negative input and a positive input of a comparator having a predetermined offset voltage. Therefore, instead of the use of a conventional two-input comparator having a voltage reference, the transistors M5 and M6 operate as a comparator.
In addition, the above offset is the same as Vgs of the transistor M0, and these two cancel each other out. Therefore, high-precision oscillation can be realized.
This kind of high-speed comparator, which is simple and has sufficient precision, is suitable for high-frequency oscillation.
In addition, oscillation frequency can be easily adjusted by tuning the resistor R0.
The capacitor C1 is referred to as a first capacitor, the capacitor C2 is referred to as a second capacitor, and the transistors M1 to M11 are referred to as first to eleventh transistors, respectively.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2024-007493 | Jan 2024 | JP | national |
