The present invention is based on Japanese Patent Application No. 2012-238984, which is incorporated herein by reference.
1. Field of the Invention
This invention relates to a relay device used in order to create an on-vehicle LAN such as an active star coupler and a connector providing the relay device.
2. Background of the Invention
The FlexRay standard which can ensure a superiority of both rapidity and liability as a next-generation on-vehicle LAN is enacted. The FlexRay is a communication protocol which is applied to in-vehicle communication requiring high liability, such as steering-by-wire, brake-by-wire, etc., in the field of automobile industry. As the FlexRay adopts a time-trigger type communication system, high liability can be maintained by designing a bus-system in which a time-slot of predetermined time is defined in a communication bus (e.g., see Japanese Unexamined Patent Application Publication No. 2009-94748, Japanese Unexamined Patent Application Publication No. 2008-277873, and Japanese Publication of PCT Application No. 2008-537430).
The FlexRay is a star type network as shown in
In recent years, there is a tendency for the number of devices connected to on-vehicle LAN (i.e., the number of nodes) to increase. Among the aforementioned two types of networks, the star type is connected in point-to-point manner, thereby realizing strength against delay and deterioration of waveform. On the other hand, due to the connection and accordingly increasing number of the nodes wire harness routing is difficult to decrease.
If the FlexRay is used as a replacement of a conventional CAN (Controller Area Network), it is necessary to connect a lot of nodes with the bus type network. In this case, inserting an ASC between PSCs as shown in
Although in
Accordingly, this invention has an object to provide a relay device and a connector including the relay device in order to increase the number of connecting nodes at a bus type network.
The invention described in claim 1 to solve the aforementioned object is a relay device which includes, in the relay device which receives an input signal and processes the input signal to transmit an output signal, a bit width distortion correction portion subjecting the input signal to bit width distortion correction for each bit unit, a ringing pulse eliminating portion subjecting the signal corrected in the bit width distortion portion to ringing pulse of a terminus of the input signal elimination.
The invention described in claim 2, in the invention described in claim 1, is characterized that the input signal includes a signal indicating a head of a data, and the bit width distortion correction portion detects the signal indicating the head of the data and generates the sampling signal to sample the input signal for each bit unit according to the signal indicating the head of the detected data as a reference.
The invention described in claim 3, in the invention described in claim 2, is characterized that the bit width distortion correction portion samples at the center of 1 bit duration of the input signal.
The invention described in claims 4-6, in the invention described in any one of claims 1-3, is characterized that the input signal includes a signal indicating a terminus of a data, and the ringing pulse eliminating portion fixes a signal level of signals continued to the signal indicating the terminus of the data to a predetermined level, when the ringing pulse eliminating portion detects the signal indicating the terminus of the data.
The invention described in claims 7-12, in a connector including a connection portion with a mating connector, is characterized to provide a relay device described in any one of claims 1-6.
According to the invention described in claim 1 described above, the relay device includes the bit width distortion correction portion subjecting the input signal to bit width distortion correction for each bit unit, the ringing pulse eliminating portion subjecting the signal corrected in the bit width distortion portion to ringing pulse of a terminus of the input signal elimination. For this reason, in order to capable of waveform shaping of not only voltage axis direction but a time axis direction, influences of bit width distortion in the relay device and ringing pulses in a terminus of the input signal may be minimized, and the number of connection nodes may be increased.
According to the invention described in claim 2, the input signal includes a signal indicating a head of data, and the bit width distortion correction portion detects the signal indicating the head of the data and generates a sampling signal to sample the input signal for each bit unit according to the signal indicating the head of the detected data as a reference. As a result, when the signal indicating the head of the data is detected, the input data may be sampled at fixed intervals, and bit width distortion may be corrected with small delay.
According to the invention described in claim 3, the bit width distortion correction portion samples at the center of 1 bit duration of the input signal. As a result, in order to capable of sampling where influences of the bit width distortion becomes the smallest, influences of bit width distortion may be minimized.
According to the invention described in claims 4-6, the input signal includes a signal indicating a terminus of a data, and the ringing pulse eliminating portion fixes a signal level of signals continued to the signal indicating the terminus of the data to a predetermined level, when the ringing pulse eliminating portion detects the signal indicating the terminus of the data. For the reason, an extension of the frame depending on the influences of ringing pulses after the terminus of the data may be prevented.
According to the invention described in claim 7-12, the relay device described in any one of claims 1-6 is provided for the connector including the connection portion with a mating connector. For the reason, functions of the relay device may be provided to the connector connecting wire harnesses with each other. Furthermore, the connector that influences of bit width distortion and ringing pulses may be minimized and the number of connection nodes may be increased is provided. Also, restrictions of mounting position of the relay device are eased by making the connector have functions of the relay device. As a result, flexibility of routing of the wire harness is enhanced.
Next, an exemplary embodiment will be described with reference to
The ASC 1 includes a bus driver BD and a control circuit 12. The control circuit 12, as shown in
The clock circuit 13 generates a 40 MS/s (40 mega sampling per seconds) clock signal and provides the noise eliminating circuit 14, the bit width distortion correction circuit 15, and the ringing pulse absorption circuit 16 with the clock signal. In this embodiment, a clock signal of 50 ns (nano seconds) frequency is generated and applied as a clock signal of 40 MS/s by sampling at both rising and falling edges.
The noise eliminating circuit 14 includes a digital filter eliminating radiation noise and conduction noise from outside. In order to prevent error-sampling depending on impulse noise which is generated by influences of radiation noise and conduction noise from outside, the impulse noise is eliminated by majority decision processing of coinciding with two times in three sampling.
A bit width distortion correction portion 15, as shown in
The 25 ns sampling signal generating portion 21 samples the input signal (input data) by a 40 MS/s clock signal provided from the clock circuit 13, and outputs the sampled input signal to a transmitting signal generating portion 24.
The BSS detection portion 22 detects a BSS (Byte Start Sequence) as a signal indicating a head of data which is included in a communication frame of the FlexRay, and outputs a signal indicating to detect (BSS detection signal) to a transmitting data-sampling signal generating portion 23.
The transmitting data-sampling signal generating portion 23 generates a transmitting data-sampling signal described later as a BSS detection signal outputted by the BSS detection portion and outputs to the transmitting signal generating portion 24.
The transmitting signal generating portion 24 further samples the input signal which is sampled in the 25 ns sampling signal generating portion 21 based on a transmitting data sampling signal which is generated in the transmitting data sampling signal generating portion 23, and the sampled signal becomes an output signal of the bit width distortion correction circuit 15.
The ringing pulse absorption circuit 16 as a ringing pulse eliminating portion, as shown in
The 25 ns sampling signal generating portion 31 samples the input signal (input data) by a 40 MS/s clock signal provided from the clock circuit 13, and outputs the sampled input signal to the ringing pulse eliminating portion 33.
The FES detection portion 32 detects a FES (Frame End Sequence) as a signal indicating a terminus of data which is included in the communication frame of the FlexRay, and outputs a signal indicating to detect (FES detection signal) to the ringing pulse eliminating portion 33.
The ringing pulse eliminating portion 33 absorbs and eliminates a ringing pulse of a frame terminus to the input signal which is sampled in the 25 ns sampling signal generating portion 31, when the FES detection signal is detected in the FES detection portion 32, and the eliminated signal becomes the output signal of the ringing pulse absorption circuit 16.
The input Ch selector 17 is connected with a Ch 1 ASC terminal and a Ch 2 ASC terminal, detects either the Ch 1 ASC terminal or the Ch 2 ASC terminal as an input, and outputs to the noise eliminating circuit 14 as a input signal R×D. Further, the selector 17 detects a TSS described later of the communication frame, generates an R×EN signal described later, and outputs to the noise eliminating circuit 14, the bit width distortion correction circuit 15 and the ringing pulse absorption circuit 16. Also, the selector 17 outputs information that either the Ch1 ASC terminal or the Ch 2 ASC terminal is as an input.
The output Ch selector 18 is connected with the Ch1 ASC terminal and the Ch2 ASC terminal, and sets a non-input terminal as an output based on information which either the Ch 1 ASC terminal or the Ch 2 terminal from the input Ch selector is an input.
Incidentally, the R×EN signal may provide separately an R×EN signal generating circuit which is in connection with the Ch 1 ASC terminal and the Ch 2 ASC terminal without generating from the input Ch selector 17, and may have a function that the bus driver BD generates the R×EN signal. Although this embodiment describes an example that the ASC 1 has two channels, three or more channels may be applied.
Next, a structure of the communication frame of the FlexRay will be described with reference to
As mentioned above, in the transmitting data, the BSS is inserted by byte units; 1 byte sequence is formed by a total of 10 bits of the transmitting data consisting of the BSS and 1 byte. Also, a bit width B which is 1 bit is 200 ns (5 M bps). The communication frame is sandwiched in an interval that a valid data is not transmitted which is called an idle state. Although the idle state is set a high level (“Hi”), at the time of output from the bus driver BD to outside, the idle state becomes an intermediate level between the high level (“Hi”) and the low level (“Lo”).
Next, an operation of a function which corrects bit width distortion in a bit width distortion correction circuit 15 will be described with reference to a timing chart of
The input signal (R×D) in
The 25 ns sampling signal, in the 25 ns sampling signal generating portion 21, is a signal sampled the R×D by 40 MS/s clock. As shown in
The BSS detection is a BSS detection signal that the BSS detection portion 22 outputs. The BSS detection detects a transition (falling) from the high level (“Hi”) to the low level (“Lo”) of the BSS. As a result, a pulse signal outputs once. The transmitting sampling signal outputs one pulse after 5 times sampling interval by 40 MS/s clock based on BSS detection. Then, total 10 pulses are outputted by 8 times sampling interval (1 bit interval). As a result, the transmitting data sampling signal may be located to the center of 1 bit interval (the fifth time in 8 times sampling).
An output signal (T×D) is a signal which is the 25 ns sampling signal re-sampled with the transmitting data sampling signal. Namely, the T×D is generated to the 25 ns sampling signal by using a transmitting signal data sampling signal as a strobe signal (which is a point of bit sampling in
In this way of generating the T×D, for example, if there is a bit width distortion d in the R×D of
Next, an operation of a function to eliminate ringing pulses will be described with reference to a timing chart of
A bus waveform of an ASC receiving side in
The bus waveform of the ASC receiving side is disturbed by influence of ringing pulses, while the waveform moves to a signal level of the idle state after the FES, as shown in
According to the embodiment, the ASC 1 includes the bit width distortion correction circuit 15 and the ringing pulse absorption circuit 16. As a result, the bit width distortion correction circuit 15 may correct bit width distortion, the ringing pulse absorption circuit 16 may absorb and eliminate ringing pulses of a terminus of the communication frame, and shape the waveform of time axis direction as a countermeasure of the bit width distortion and the extension of the communication frame. Therefore, the influence of bit width distortion and the ringing pulses at the ASC 1 may be minimized, and the number of connection nodes may be increased.
The bit width distortion correction circuit 15 detects the BSS, generates a transmitting data sampling signal to locate at the center of 1 bit interval based on the detected the BSS, and samples the input signal for each bit unit as the transmitting data sampling signal is a strobe signal. Therefore, if the BSS is detected, the input data may be sampled at fixed intervals at the center of the bit interval, and the bit width distortion may be corrected with small delay. In aforementioned embodiment, although an example that 1 bit interval becomes longer depending on bit width distortion is described, when 1 bit interval becomes short, the bit width distortion may be corrected by sampling at the center of 1 bit interval.
The bit width distortion correction circuit 15 generates a transmitting data by sampling at every 1 bit interval of the transmitting data sampling signal. As a result, the process may be done at every 1 bit, and the bit width distortion may be corrected with small delay.
The bit width distortion correction circuit 15 generates the transmitting data sampling signal based on the detection of the BSS. As a result, to retake a basis at every 10 bits of both the BSS and 1 byte may prevent the sampling error, etc. from accumulating.
When the ringing pulse absorption circuit 16 detects the FES, the signal level of the FES transition is fixed to “Hi”. For this reason, the extension of the communication frame depending on the influence of ringing pulses after the FES may be prevented.
Furthermore, the aforementioned structure of the ASC 1 may be implemented to an intermediate connector.
The connector housing 41 is formed in a flat box shape and made of insulating synthetic resin, etc. One side of the housing is attached the wire harness 43 which is formed of several electric wires, which includes a core wire at one side and a covering portion covering the core wire. The other side which is engaged with the mating connector 50 is recessed to accommodate the mating connector 50. In the rear side of the recess, a terminal 42 is provided as a connection portion.
The ASC 1 is accommodated in the connector housing 41 and electrically connected with the terminal 42 and the wire harness 43. In other words, either one of the terminal 42 or the wire harness 43 becomes a receiving side, or the other becomes a transmitting side.
The mating connector 50 includes a connector housing 51 and a wire harness 52. The connector housing 51 is formed in a flat box shape and made of insulating synthetic resin, etc. One side of the housing is attached the wire harness 52 which is formed of several electric wires, which includes a core wire at one side and a covering portion covering the core wire. In the other side which is engaged with the intermediate connector 40, connected means which are not illustrated are provided and electrically connected in the wire harness 52 and the connector housing 51.
The ASC 1 is incorporated to the intermediate connector 40 as shown in
In the aforementioned embodiment, the transmitting data sampling signal may be not the fifth time but the fourth time in 8 times sampling during 1 bit interval. In other words, the signal may be the center of the 1 bit interval. In addition, the center does not mean to restrict only 100 ns position when 1 bit interval is 200 ns, but means a bit sampling point close to 100 ns. Therefore the fourth time and fifth time of the aforementioned embodiment becomes the center. Also, the input signal samples 8 times during 1 bit interval. Needless to say, the sampling is not restricted to 8 times.
In the aforementioned embodiment, the FlexRay as a communication protocol is described. However, the communication protocol which is a serial data transfer of bus format and includes a data corresponding to the BSS or the FES may be applied.
Furthermore, the aforementioned embodiments are only shown some representatives of this invention, and this invention is not limited of these embodiments. Therefore, it can be performed with several changes without deviating from the scope of this invention.
Number | Date | Country | Kind |
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2011-105801 | May 2011 | JP | national |
Number | Date | Country | |
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Parent | PCT/JP2012/061709 | May 2012 | US |
Child | 14076740 | US |