Relay unit and storage medium having stored therein computer program

Abstract

A relay unit capable of avoiding the occurrence of simultaneous switching whatever data is received and thereby preventing malfunction of the device due to impulse noise, and a memory product having stored therein a computer program are provided. The relay unit includes a latch unit that temporarily stores converted parallel data; a determining unit that compares received data with subsequent data to be received subsequently and thereby determines whether to invert bits of data; and an inverting unit that invert bits of converted serial data. When the determining unit determines that bit-inverted parallel data is received as subsequent data, the determining unit transmits to the latch unit a signal instructing to prohibit from storing temporarily the received subsequent data and transmits to the inverting unit a signal instructing to invert bits of data.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a conventional relay unit;

FIG. 2 is a block diagram showing a configuration of a relay unit according to a first embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of an encoding unit;

FIG. 4 is a block diagram showing a configuration of a decoding unit;

FIG. 5 is a block diagram showing a configuration of a determining unit;

FIG. 6 is a block diagram showing an operation of the relay unit performed when data P matches data Q;

FIG. 7 is a block diagram showing a configuration of a relay unit according to a second embodiment of the present invention, where data of an X frame is received;

FIG. 8 is a block diagram showing a configuration of a determining unit;

FIG. 9 is a block diagram showing an operation of the relay unit performed when data P matches data Q;

FIG. 10 is a block diagram showing a configuration of a microcomputer that composes a receive block of a relay unit according to a third embodiment of the present invention;

FIG. 11 is a block diagram showing a configuration of a microcomputer that composes a transmit block of the relay unit according to the third embodiment of the present invention;

FIG. 12 is a flowchart showing processing steps of a CPU of the microcomputer that composes the receive block of the relay unit according to the third embodiment of the present invention;

FIG. 13 is a flowchart showing processing steps of a CPU of the microcomputer that composes the transmit block of the relay unit according to the third embodiment of the present invention;

FIG. 14 is a flowchart showing processing steps of a CPU of a microcomputer that composes a receive block of a relay unit according to a fourth embodiment of the present invention; and

FIG. 15 is a flowchart showing processing steps of a CPU of a microcomputer that composes a transmit block of the relay unit according to the fourth embodiment of the present invention.

Claims

1. A relay unit which encodes data received frame by frame, converts the encoded data into parallel data, performs a predetermined process on the converted parallel data, converts the parallel data into serial data having been subjected to the predetermined process, decodes the converted serial data, and transmits the decoded serial data to external devices, comprising: a latch unit that temporarily stores, frame by frame, converted parallel data;a determining unit that compares received data with subsequent data to be received subsequently and thereby determines whether to invert bits of data; andan inverting unit that invert bits of converted serial data, whereinthe determining unit comprises:means for determining whether data obtained by inverting bits of the received converted parallel data is received as subsequent data;means for transmitting, in case for determining that the data is received as subsequent data, a signal instructing to prohibit from storing temporarily the received subsequent data, to the latch unit; andmeans for transmitting to the inverting unit a signal instructing to invert bits of data.

2. The relay unit according to claim 1, wherein the determining unit further comprises:means for determining whether data obtained by inverting bits of part of the received converted parallel data is received as subsequent data;means for transmitting, in case for determining that the data is received as subsequent data, a signal instructing to prohibit from storing temporarily the received subsequent data, to the latch unit; andmeans for transmitting to the inverting unit a signal instructing to invert a bit which has not been inverted and to prohibit from inverting other bits.

3. The relay unit according to claim 1, wherein the determining unit further comprises:means for temporarily storing the received converted parallel data and the subsequent converted parallel data received subsequently.

4. The relay unit according to claim 2, wherein the determining unit further comprises:means for temporarily storing the received converted parallel data and the subsequent converted parallel data received subsequently.

5. A relay unit that encodes data received frame by frame, converts the encoded data into parallel data, performs a predetermined process on the converted parallel data, converts the parallel data into serial data having been subjected to the predetermined process, decodes the converted serial data, and transmits the decoded serial data to external devices, comprising: a latch unit that temporarily stores, frame by frame, converted parallel data;a determining unit that compares received data with subsequent data to be received subsequently and thereby determines whether to invert bits of data; andan inverting unit that invert bits of converted serial data, whereinthe determining unit comprises a processor capable of performing steps ofdetermining whether data obtained by inverting bits of the received converted parallel data is received as subsequent data;transmitting, in case for determining to be received as subsequent data, a signal instructing to prohibit from storing temporarily the received subsequent data, to the latch unit; andtransmitting to the inverting unit a signal instructing to invert bits of data.

6. The relay unit according to claim 5, wherein the determining unit comprises the processor further capable of performing steps of:determining whether data obtained by invert bits of part of the received converted parallel data is received as subsequent data;transmitting, in case for determining to be received as subsequent data, a signal instructing to prohibit from storing temporarily the received subsequent data, to the latch unit; andtransmitting to the inverting unit a signal instructing to invert a bit which has not been inverted and to prohibit from inverting other bits.

7. The relay unit according to claim 5, wherein the determining unit comprises the processor further capable of performing a step of:temporarily storing the received converted parallel data and the subsequent converted parallel data received subsequently.

8. The relay unit according to claim 6, wherein the determining unit comprises the processor further capable of performing a step of:temporarily storing the received converted parallel data and the subsequent converted parallel data received subsequently.

9. A computer memory product storing a computer program for causing a computer to: encode data received frame by frame;convert the encoded data into parallel data and perform a predetermined process on the converted parallel data;convert the parallel data into serial data having been subjected to the predetermined process; anddecode the serial data and transmit the decoded serial data to external devices, whereinthe computer program comprising the steps ofcausing the computer to temporarily store, frame by frame, converted parallel data;causing the computer to determine whether data obtained by inverting bits of the received converted parallel data is received as subsequent data; andcausing the computer to convert into serial data, in case for determining to be received as subsequent data, the received subsequent data without temporarily storing the received subsequent data and then to invert bits of data.

10. The computer memory product storing a computer program according to claim 9, the computer program further comprising the steps of: causing the computer to determine whether data obtained by inverting bits of part of the received converted parallel data is received as subsequent data; andcausing the computer to transmit, in case for determining to be received as subsequent data, an instruction to convert the received subsequent data into serial data without temporarily storing the received subsequent data and then to invert a bit which has not been inverted and to prohibit from inverting other bits.