Patent Application
20070061500
“Flash memory” is an example of one kind of solid-state electronic memory. Flash memory is highly reliable, shock-and-vibration resistant, low-power-consuming, non-volatile memory which utilizes a relatively low-cost, high-density, high-speed architecture. Flash memory does not need a constant power supply to retain its data and it offers extremely fast access times. These qualities combined with its compact size, make flash memory desirable for scanners, printers, video game consoles, digital cameras, mobile phones, pagers, handheld computers, and other portable devices.
As is typical for conventional flash memory devices, the flash memory system 130 of
The secondary data storage area are supernumerary data resources 134. Generally, “supernumerary” means exceeding a fixed, prescribed, or standard number or amount. Herein, the supernumerary data resources are specifically those resources that are typically accessed outside the full range of addressable memory available to the primary main array memory 132. Herein, the supernumerary data resources 134 expressly include memory and non-memory data resources. Non-memory supernumerary data resources 134 include input/output sources and data generation sources. Memory supernumerary data resources 134 expressly includes array and non-array memory.
The access-mode switch logic 136 determines whether an incoming memory-access request will retrieve data from the primary main array memory 132 or the secondary supernumerary memory 134. When a flash memory device is in a main array “access-mode,” it responds to a memory access with the content located at a designated memory location in the primary main array memory 132. When the flash memory is in the secondary access-mode, it responds with data content found in the secondary supernumerary memory 134.
Typically, the processing core 120 is mode-agnostic. When the processing core submits an access request, the core is not aware of “access-modes.” Instead, one or more higher level components (e.g., a BIOS device driver or operating system) selects the access-mode of the flash memory system 130. If this higher-level component and the flash memory system gets “out of synch,” then it is possible for the processing core to retrieve data from the secondary supernumerary memory 134 when it expects to retrieve data from the main array memory 132 and vice versa.
In conventional approaches, strategies were implemented to reduce the chances of the flash memory being in an unexpected mode. Interrupts demand immediate action by the mode-agnostic processing core 120 and may cause it to access memory without a needed change of access-mode. Therefore, one conventional approach is to mask incoming interrupts and place them in the interrupt queue 124.
Consequently, interrupts are not immediately recognized and serviced. Instead, mode-aware higher-level components periodically examine the interrupt queue 124. These mode-aware higher-level components release pending interrupts and, if necessary, switch the access-mode of the flash memory before releasing pending interrupts.
The same numbers are used throughout the drawings to reference like elements and features.
Rather than switching access-modes of a flash memory system between a primary main array memory and a secondary supernumerary data resource, one or more implementations, described herein, provides access to the secondary supernumerary data resource through an overlay window in the primary main array memory. One or more of the described implementations sacrifice a relatively tiny defined address space of the primary main array to act as this overlay window. Access to a memory location within this overlay window are redirected to the secondary supernumerary data resource.
Since the sacrificed address space of the primary main array memory is inaccessible when the overlay window is active, the overlay window is re-locatable. With knowledge of the high-level organizational structure of the data in the primary main array memory, one or more of the described implementations select a present location of the overlay window which is unlikely to be accessed given a present status of the high-level systems (e.g., operating system) of the computing device utilizing the flash memory system.
One or more of the described implementations simplifies system software integration and reduces interrupt latency by keeping the vast majority of contents of the main-array memory accessible at all times.
When compared to the traditional approach that switches access-modes to access the two separated data resources (e.g., main array memory and secondary supernumerary data resources), the new approach provided by one or more implementations described herein simplifies system software integration by eliminating or ameliorating the need to:
Box 210 includes some of the relevant components of one or more implementations. These depicted components include at least one processing core 220 which includes essential processing components (e.g., one or more processors) and related memory systems), a communications bus 222, and a flash memory system 230. The processing core 220 communicates with the flash memory system 230, and other unspecified components (not shown) via the bus 222. Since an interrupt queue is unnecessary in one or more implementations described herein, there is no interrupt queue depicted in
The flash memory system 230 of
The supernumerary data resources 234 are typically those that accessed outside the full range of addressable memory available to the primary main array memory 232. Herein, the supernumerary data resources 234 expressly include memory and non-memory data resources. Non-memory supernumerary data resources 234 include input/output sources and data generation sources, such as dynamic output of arithmetic circuits and noise-based pseudorandom number generators. Memory supernumerary data resources 234 expressly includes array and non-array memory. For example, the memory supernumerary data resources 234 may include secondary arrays of Flash memory and/or SRAM memory.
In one or more implementations described herein, the supernumerary data resources 234 is a non-array memory, which includes, for example, memory-mapped registers, SRAM buffers, flip-flops, or any other memory technology.
Typically, much of the data in non-array memory is pre-programmed or pre-set by the manufacturer of the flash memory device. By way of example only and not limitation, the data in a non-array memory contains identifier codes, common-flash-interface (CFI) datasheet-in-a-chip, one-time-programmable (OTP) serial codes. Other non-array memory contents typically are dynamic during system operation. By way of example only and not limitation, the data in an array memory contains read configuration registers, status registers, block lock flags, programming buffers, and read buffers. The storage capacity of the non-array memory is typically one or more orders of magnitude smaller than the storage capacity of a main array memory.
With the one or more implementations, the flash memory system 230 no longer needs access-mode switch logic like that depicted at 136 in
The overlay window manager 240 defines an address space in the primary main array memory 232 to act as this supernumerary overlay window 250. Therefore, when the processing core 220 attempts to access a memory address within that defined address space in the primary main array memory, that access is redirected to the secondary supernumerary data resource 234 instead. This redirection is illustrated by double-headed arrow 252 in
Because of this redirection, the flash memory system 230 never needs to change modes like the traditional approach illustrated in
However, the overlay window manager 240 sacrifices an otherwise addressable memory space in the primary main array memory 232 when it defines the supernumerary overlay window 250 to exist over that addressable memory space. The data in that sacrificed address space of the primary main array memory 232 is inaccessible when the supernumerary overlay window 250 is active.
To expose the “hidden” data behind the supernumerary overlay window 250, the window is re-locatable within the primary main array memory 232. With knowledge of the high-level organizational structure of the data in the primary main array memory 232, the overlay window manager 240 (and/or one or more higher-level components such as a BIOS driver or operating system) select a new location for the overlay window making inaccessible a region of the primary main array memory which is unlikely to be accessed given a present status of the high-level system (e.g., operating system) of the computing device utilizing the flash memory system 230.
Typically, the data in the primary main array memory 232 is logically divided into multiple segments of contiguous memory. For example, there may be one segment for loading an operating system, another segment for low-level operating system software (i.e., kernel), another segment for data, and perhaps another segment for executable instructions. It is also common for a computing device employing a flash memory system to operate in multiple states, phases, or cycles. For example, the phases may include the initial power-up, the loading of initial system software, normal operation, etc. Typically, it is common for the frequency of memory access for each segment to vary relative to the present operating phase of the computer device.
While the above embodiments focus on the present operating phase of the computer device as a trigger for relocation of the supernumerary overlay window, there may be other factors that could cause a relocation trigger. By way of example only (and not limitation) the following are other exemplary independent triggers:
Phase-1 representation 300 depicts the initial power-up of the device. In this representation, the memory is logically divided into interrupt vectors segment 302, bootloader segment 304, OS kernel segment 306, and file system data segment 308. In Phase-1, there is no need yet for an overlay window; so, none is shown in the phase-1 representation 300.
Phase-2 representation 310 depicts the system boot cycle of the device. In this representation, the memory is logically divided into interrupt vectors segment 312, bootloader segment 314, OS kernel segment 316, and file system data segment 318. During this phase, the processing core 220 will not yet be accessing data in the OS kernel segment 316. Therefore, the overlay window manager 240 places a supernumerary overlay window 330 in the OS kernel segment 316.
Phase-3 representation 320 depicts normal operating state of the device. This is after booting and the OS kernel is now operating. In this representation, the memory is logically divided into interrupt vectors segment 322, bootloader segment 324, OS kernel segment 326, and file system data segment 328. During this phase, the processing core will no longer be accessing data in the bootloader segment 324 because the device has already completed the boot process. Therefore, the overlay window manager 240 places a supernumerary overlay window 340 in the bootloader segment 324.
As shown in
Register 440 represents a mode register. A sub-register demux 442 determines which sub-register is being accessed within the mode register. When the MRS bits are set to “01,” then data being written to or read from the register 440 is the “mode register 01.” More particularly, the value being written to or read from the register 440 in these instances is the starting location of the defined address space for the overlay window.
Methodological Implementation
At 502 of
At 504, the manager 240 assigns the location (e.g., a defined address space) of the supernumerary overlay window (such as window 250) within one of multiple logically organized segments of contiguous memory in the main array memory. For example, as shown in
However, depending upon the phase, it may be desirable to leave a supernumerary overlay window unassigned and undefined. This may be desirable when there is no need to access the data found in the non-array memory. This situation is illustrated by the Phase-1 representation 300 of
At 506, the manager 240 intercepts any incoming memory access (e.g., read or write) into the defined address space designated for the supernumerary overlay window. Therefore, such memory access will not gain access to the content in the main array memory that is “hidden” behind the overlay window.
At 508, the manager 240 redirects the intercepted access to the secondary supernumerary data resources instead of the main array memory. Therefore, this intercepted access will read/write data from/to the secondary supernumerary data resources rather than the main array memory. Furthermore, it does this without requiring the flash memory hardware to change “access-modes.”
At 510, the manager 240 (or some other component of a device implementing a flash memory system like system 230—which includes a software component) determines if there has been a change in the operational phase. If so, then the entire process repeats by going back to block 502 to determine the current operating phase. If not, then the process maintains a loop back to block 506 to continuously check for incoming memory accesses into the overlay window.
The above discusses changes in operational phases as being the trigger to relocate the supernumerary overlay window. However, this is just one or many possible implementations. Those of skill in the art understand that other behaviors, actions, or conditions may trigger a relocation of the overlay window. In general, a relocation trigger may occur when a change in conditions occurs so that another memory segment (other than the one that the window currently resides) becomes the least likely segment to be accessed.
Conclusion
The techniques, described herein, may be implemented in many ways, including (but not limited to) program modules, general- and special-purpose computing systems, network servers and equipment, dedicated electronics and hardware, and as part of one or more computer networks.
Although the one or more above-described implementations have been described in language specific to structural features and/or methodological steps, it is to be understood that other implementations may be practiced without the specific features or steps described. Rather, the specific features and steps are disclosed as preferred forms of one or more implementations.
