In memory systems, two general classes of memories exist. Such classes include low latency memories. The low latency memories have effectively infinite endurance or usage-cycles and do not degrade with respect to age or repeated accesses. Additionally, such classes also include relatively longer latency memories that do not have infinite endurance or usage cycles, and may degrade with respect to age or repeated accesses. In the case of the relatively long latency memories, sophisticated multi-error detection and correction algorithms have been implemented to correct for data cells that can degrade over the lifetime of the device due to aging effects or repeated accesses. In the case of low latency memories such as dynamic random access memory (“DRAM”) devices, however, effectively infinite endurance or usage-cycles are assumed so once weak bits or bad bits are mapped out by the device manufacturer, no errors should occur due to degradation of data cells due to aging effects or repeated accesses. Although highly successful, low latency memories have limitations.
A trend in the development of memory storage devices is that as the storage cells continue to shrink due to advancements in process technology, storage cells in low latency memories such as DRAM devices may become more susceptible to errors that occur due to aging effects or repeated accesses. Moreover, the number of weak bits due to natural process variations will continue to increase. Accordingly, it is desirable that spare storage cells can be utilized to correct for the presence of faulty storage cells in low latency memory that may develop over the lifetime of the device.
A system and method are provided for replacing faulty or weak memory storage cells in a memory system through the use of an enhanced memory interface circuit or enhanced memory controller device and the use of redundant memory storage cells. Further details of the present system and method can be found throughout the present specification and more particularly below.
The present invention provides for a method that may be implemented in different ways for different systems. An implementation is described herein as an illustrative example. The example should not be construed as limiting the scope of the claims according to the present invention.
Example: Utilizing an Address Match Table in Memory Interface Circuit, Controlling Spare Memory Storage Cells to Dynamically Replace Faulty Storage Cells in Memory Devices, as illustrated by
In other implementations, address fields for Chip ID (CID) and Bank Group ID may also be used. The addresses of faulty or weak memory storage cells contained in the Address Match Table may be determined by testing during manufacturing or special run-time testing. The entries in the Address Match Table may also be dynamically updated during runtime if it is determined that additional memory storage locations are weak or faulty. The function of the Address Match Table is to act as a filter of addresses and commands that flow through the enhanced memory interface circuit 110. In the case that a given memory access is matched to an entry in the Address Match Table, the Address Match Table replaces the address of the memory access with the address of a spare memory location. In this manner, the existence of the faulty or weak memory address is hidden from the host memory controller, and the enhanced memory interface circuit enables the memory devices to present a contiguous memory address space without faulty or weak cell locations, as shown in
It should be understood that the description recited above is an example of the disclosure and that modifications and changes to the examples may be undertaken which are within the scope of the claimed disclosure. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements, including a full scope of equivalents.
Number | Date | Country | |
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61535780 | Sep 2011 | US |