The subject matter described herein relates generally to systems, devices, and methods for the protection and coordination of electrical power system, and more particularly with an emphasis in estimating the level of incident energy or thermal arc-flash or arc-fault energy in a time-current curve or time-current characteristic plot (TCC) using bounded area regions defined by all arc fault or arc-flash input parameter variations. The subject matter described herein applies to electrical power systems for utilized in any scientific field or any industry which utilizes electrical energy (e.g. research laboratories, manufacturing, power generation, aviation, transportation, etc.).
The electrical power industry has experienced a huge growth area in the field of arc-flash analysis. The last two decades have seen the onset and sunset of IEEE 1584-2002, the theoretically derived Ralph Lee method and several other methods for the calculation of incident energy from arc flash events. Traditionally arc-flash incident energy or arc fault energy in general is determined based on a “single-set” of input parameters regardless of the selected calculation equations. Typically, the output of the calculations is a single point combination of current and time or a single line which represents the incident energy or arc thermal energy value.
Thus, needs exist for improved systems, devices, and methods for the protection and coordination of electrical power system, and more particularly with an emphasis in estimating the level of incident energy or thermal arc-flash or arc-fault energy in a time-current characteristic plot (TCC), and for improving short-circuit analysis, protective device coordination and protection, and arc-flash analysis.
Provided herein are example embodiments of systems, devices and methods to create and visualize an arc-flash incident energy or arc fault thermal energy on a TCC plot. In some embodiments, the system may use an area shape or region (of any form) on a TCC plot. The bounded area may represent a reference constant or variable arc fault energy or arc flash incident energy value. In some embodiments, the bounded area may be derived from all, or substantially all, combinations and variations of the input parameters of AC, DC and multi-frequency arc faults or arc flash which yield a constant energy (equipment energy damage) or constant incident energy level (for personnel thermal hazard evaluation). The bounded amorphous area may represent any combination of possible input parameter variation which causes the arc fault or arc-flash to release the reference constant energy value.
As used herein, constant energy means reference energy value (equipment damage) or incident energy (for personnel thermal energy exposure) in Joule/cm{circumflex over ( )}2/sec or Joule/sec.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Moreover, it is noted that the invention is not limited to the specific embodiments described in the Detailed Description and/or other sections of this document. Such embodiments are presented herein for illustrative purposes only. Additional features and advantages of the invention will be set forth in the descriptions that follow, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description, claims and the appended drawings.
The present invention may be better understood by referring to the following figures. The components in the figures are not necessarily to scale. Emphasis instead being placed upon illustrating the principles of the disclosure. In the figures, reference numerals designate corresponding parts throughout the different views.
The following disclosure describes various embodiments of the present invention and method of use in at least one of its preferred, best mode embodiment, which is further defined in detail in the following description. Those having ordinary skill in the art may be able to make alterations and modifications to what is described herein without departing from its spirit and scope. While this invention is susceptible to different embodiments in different forms, there is shown in the drawings and will herein be described in detail a preferred embodiment of the invention with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the broad aspect of the invention to the embodiment illustrated. All features, elements, components, functions, and steps described with respect to any embodiment provided herein are intended to be freely combinable and substitutable with those from any other embodiment unless otherwise stated. Therefore, it should be understood that what is illustrated is set forth only for the purposes of example and should not be taken as a limitation on the scope of the present invention.
In the following description and in the figures, like elements are identified with like reference numerals. The use of “e.g.,” “etc.,” and “or” indicates non-exclusive alternatives without limitation, unless otherwise noted. The use of “including” or “includes” means “including, but not limited to,” or “includes, but not limited to,” unless otherwise noted.
As used herein, the term “and/or” placed between a first entity and a second entity means one of (1) the first entity, (2) the second entity, and (3) the first entity and the second entity. Multiple entities listed with “and/or” should be construed in the same manner, i.e., “one or more” of the entities so conjoined. Other entities may optionally be present other than the entities specifically identified by the “and/or” clause, whether related or unrelated to those entities specifically identified. Thus, as a non-limiting example, a reference to “A and/or B,” when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including entities other than B); in another embodiment, to B only (optionally including entities other than A); in yet another embodiment, to both A and B (optionally including other entities). These entities may refer to elements, actions, structures, steps, operations, values, and the like.
As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.
In general, terms such as “coupled to,” and “configured for coupling to,” and “secure to,” and “configured for securing to” and “in communication with” (for example, a first component is “coupled to” or “is configured for coupling to” or is “configured for securing to” or is “in communication with” a second component) are used herein to indicate a structural, functional, mechanical, electrical, signal, optical, magnetic, electromagnetic, ionic or fluidic relationship between two or more components or elements. As such, the fact that one component is said to be in communication with a second component is not intended to exclude the possibility that additional components may be present between, and/or operatively associated or engaged with, the first and second components.
Generally, the present disclosure provides systems, devices and methods for creating and visualizing an arc-flash incident energy or arc fault thermal energy on a TCC plot. In some embodiments, the system may use an area shape or region (of any form) on a TCC plot. The area may be bounded and may represent a reference constant or variable arc fault energy or arc flash incident energy value. In some embodiments, the system may derive the bounded area from all, or substantially all, combinations and variations of the input parameters of AC, DC and multi-frequency arc faults or arc flash which yield a constant energy (equipment energy damage) or constant incident energy level (for personnel thermal hazard evaluation). The bounded amorphous area may represent any combination of possible input parameter variation which causes the arc fault or arc-flash to release the reference constant energy value. This is a new concept and totally innovative way to visualize arc-flash incident energy or thermal energy released by an arc when compared to the single set of input parameter representation being used by the industry now (as shown in
The innovative boundary area algorithm, as shown below, has at least two major innovations which include the consideration of a very high number (e.g., in the thousands since the number of variations may be determined by the number of range variation raised to the number of input parameters. For example, taking 3{circumflex over ( )}7 or 2187 combinations as minimum and 4{circumflex over ( )}9 or 262,144 as a potential higher end number of combinations. The higher the number of parameters, the higher the number of combinations) of combinations of input parameters plus all the variations in each of the input parameters. In some embodiments, variations may mean how each parameter is changed along a range of changes. For example, there may be 7 input parameters and the system may apply a ±10% variation with a step size of 10%. This would make it 3{circumflex over ( )}7 potential solutions. The above provides a way to visualize the arc or arc-flash in a way that cannot be accomplished by any algorithm which only uses one set of input parameters. The region may also provide a probabilistic solution, (i.e., which combinations of the variations on input parameters and which ones are most likely to occur), within the bounded region or boundary. For example, there may be 2187 combinations, the algorithm may determine that 1000 of those have a 50% probability of occurring and so on
In some embodiments, to derive the C-arc plots, the system may use multiple combinations of input parameters which vary for arc faults or arc-flash calculations. The input parameters may include, for example, one or more of:
1. Voltage (AC or DC voltage variations)
2. Current (AC or DC bolted fault current level or available fault current)
3. Gap between conductors (constant gap or as a function of time)
4. Conductor arrangement, layout, orientation, electrode configurations, or any conductor positioning or arrangement supported by various ANSI or IEC standards for arc-flash energy calculations.
5. Conductor material (variations in conductor materials such as copper or aluminum)
6. Conductor erosion rate (the rate of erosion of material under different arc power)
7. Working distance
8. Height, Width and Depth of any equipment enclosing the arc fault or arc flash
9. Ambient Temperature variation
10. Altitude and Humidity levels
11. Operating temperature of the conductors (Tc)
12. Variations in response time or opening time of protective devices which de-energize the arc fault or arc-flash represented by the amorphous bounded area shape of constant incident energy
13. Arc-current variation and probabilistic changes in the arc-current magnitude related to variations in operating voltage, gap between conductors and conductor arrangement or orientation
14. Operating system frequency (any system frequency including 50/60 Hz).
Ax=f(ΔEC,(Iarc+ΔIarc),Itfxr(Voc+ΔVoc),(G+ΔG),k1 to k10,
(T+ΔT)xr(D+ΔD), (ΔCF), k1 to k13, ΔTa, ΔTc, ±ΔF, . . . ) delta changes are inputs which affect or describe the arc behavior. Examples of all the variations considered (not limited to the list) are:
±ΔVoc System voltage variation (p.u.)
±ΔG Pos. or neg. variation in Gap (p.u.)
±ΔD Working distance variation (p.u.)
±ΔCF Enclosure size correction factor (p.u.)
ΔEC Electrode Config. (VCB, VCBB, HCB)
|ΔIarc| Arc current variation (p.u.)
±ΔTk Ambient temperature variation (p.u.)
±ΔF System Frequency variation for a.c. systems (p.u.)
The derived region provides information on the potential operating points of the arc, duration of the fault, limits of the expected arc current, arc resistance and arc voltage, the required pickup settings of protective devices used to prevent damage to the equipment/personnel, the variation in current and time if the arc occurs under different electrode/conduction configurations (ΔEC), etc.
In some embodiments, the system may use the bounded area regions defined by all arc fault or arc-flash input parameter variations to estimate the worst-case incident energy during the short-circuit/protective device coordination and protection stage. The present disclosure may allow consideration of many probabilistic and deterministic variations in the physical parameters which are inputs to the calculation of the arc-flash incident energy.
In some embodiments, the system and method of the present disclosure may visualize the incident energy level which could be released in the event of an arc-flash or arc fault in a power system electrical equipment. The visualization may be done on a TCC plot as shown above.
Some examples of applications using the systems and methods of the present disclosure are now presented.
The constant incident energy bounded area or region plots can be used to represent constant incident energy levels in TCC when applied with any arc-flash incident energy equations. The equations may come from NFPA 70E, IEEE 1584-2002, IEEE 1584-2018, DGUV-I 203-078, EPRI, Terzija/Konglin, or any other equation with varying input parameters. Applying the innovative boundary area algorithm of the present disclosure, including the consideration of thousands of combinations of input parameters plus all the variations in each of the input parameters, bounded regions can be derived. Each region can also provide a probabilistic solution, (i.e. which combinations are most likely to occur), within the bounded region or boundary.
In the example of
The constant energy bounded area or region plots can be used to represent constant energy levels in TCC which represent the arc-damage point of the equipment. Internal arc faults can be represented as areas of constant energy which show the damage sustained to the equipment.
The constant energy bounded are or region plots can be used to represent constant energy levels in TCCs using real-time measurements of varying voltage, currents, ambient temperature, humidity, etc., which are varying input parameters recorded from a real-time system, for example a supervisory control and data acquisition (SCADA) system.
The constant incident energy bounded area or region plots can be used to represent constant incident energy levels in TCC when applied with any DC arc-flash incident energy equations. The equations may come from NFPA 70E Maximum Power Method, Paukert, Stokes or Oppenlander, EPRI DC, or any other industry accepted DC arc-flash incident energy calculation method with varying input parameters.
System Architecture
In the example of
The processing circuit 604 may be responsible for managing the bus 602 and for general processing, including the execution of software stored on the machine-readable medium 606. The software, when executed by processing circuit 604, causes processing system 614 to perform the various functions described herein for any apparatus. Machine-readable medium 606 may also be used for storing data that is manipulated by processing circuit 604 when executing software.
One or more processing circuits 604 in the processing system may execute software or software components. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. A processing circuit may perform the tasks. A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory or storage contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.
It should also be noted that all features, elements, components, functions, and steps described with respect to any embodiment provided herein are intended to be freely combinable and substitutable with those from any other embodiment. If a certain feature, element, component, function, or step is described with respect to only one embodiment, then it should be understood that that feature, element, component, function, or step can be used with every other embodiment described herein unless explicitly stated otherwise. This paragraph therefore serves as antecedent basis and written support for the introduction of claims, at any time, that combine features, elements, components, functions, and steps from different embodiments, or that substitute features, elements, components, functions, and steps from one embodiment with those of another, even if the following description does not explicitly state, in a particular instance, that such combinations or substitutions are possible. It is explicitly acknowledged that express recitation of every possible combination and substitution is overly burdensome, especially given that the permissibility of each and every such combination and substitution will be readily recognized by those of ordinary skill in the art.
To the extent the embodiments disclosed herein include or operate in association with memory, storage, and/or computer readable media, then that memory, storage, and/or computer readable media are non-transitory. Accordingly, to the extent that memory, storage, and/or computer readable media are covered by one or more claims, then that memory, storage, and/or computer readable media is only non-transitory.
While the embodiments are susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that these embodiments are not to be limited to the particular form disclosed, but to the contrary, these embodiments are to cover all modifications, equivalents, and alternatives falling within the spirit of the disclosure. Furthermore, any features, functions, steps, or elements of the embodiments may be recited in or added to the claims, as well as negative limitations that define the inventive scope of the claims by features, functions, steps, or elements that are not within that scope.
It is to be understood that this disclosure is not limited to the particular embodiments described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.
Various aspects have been presented in terms of systems that may include several components, modules, and the like. It is to be understood and appreciated that the various systems may include additional components, modules, etc. and/or may not include all the components, modules, etc. discussed in connection with the figures. A combination of these approaches may also be used. The various aspects disclosed herein can be performed on electrical devices including devices that utilize touch screen display technologies and/or mouse-and-keyboard type interfaces. Examples of such devices include computers (desktop and mobile), smart phones, personal digital assistants (PDAs), and other electronic devices both wired and wireless.
In addition, the various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
Operational aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
Furthermore, the one or more versions may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed aspects. Non-transitory computer readable media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips . . . ), optical disks (e.g., compact disk (CD), digital versatile disk (DVD), BluRay™ . . . ), smart cards, solid-state devices (SSDs), and flash memory devices (e.g., card, stick). Of course, those skilled in the art will recognize many modifications may be made to this configuration without departing from the scope of the disclosed aspects.
The present application is a continuation of International Patent Application No. PCT/US20/52071, filed Mar. 23, 2020, which claims priority pursuant to U.S.C § 119(e) to U.S. Provisional Patent Application No. 62/904,353, filed Mar. 23, 2019, the disclosures of both of which are hereby incorporated by reference in their entireties for all purposes.
Number | Date | Country | |
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62904353 | Sep 2019 | US |
Number | Date | Country | |
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Parent | PCT/US20/52071 | Sep 2020 | US |
Child | 17702615 | US |