Reset detection circuit in semiconductor integrated circuit

Abstract

A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the accompanying drawings:

FIG. 1 is a circuit diagram of a reset detection circuit according to a first embodiment of the invention;

FIG. 2 is a timing diagram showing situations that occur when a power supply is started, when a battery is instantaneously disconnected, when a voltage VDD falls due to a surge, and when the power supply stops under a condition of V-RST2>V-MIN>VDD>V-RST;

FIG. 3A is a timing diagram showing a situation that occurs when the voltage VDD rises sufficiently earlier than the voltage 5VIN does;

FIG. 3B is a timing diagram showing a situation that occurs when the voltage VDD falls sufficiently earlier than the voltage 5VIN does;

FIG. 3C is a timing diagram showing a situation that occurs when the voltage VDD rises sufficiently later than the voltage 5VIN does;

FIG. 3D is a timing diagram showing a situation that occurs when the voltage VDD falls sufficiently later than the voltage 5VIN does;

FIG. 4 is a circuit diagram of a reset detection circuit according to a third embodiment of the invention;

FIG. 5 is a circuit diagram of a conventional reset detection circuit;

FIG. 6 is a timing diagram showing a situation that occurs when the power supply is started, when the battery is instantaneously disconnected, when the voltage VDD falls due to a surge, and when the power supply stops under a condition of VDD>V-RST>V-MIN; and

FIG. 7 is a timing diagram showing a situation that occurs when the power supply is started, when the battery is instantaneously disconnected, when the voltage VDD falls due to a surge, and when the power supply stops under a condition of V-MIN>VDD<V-RST.

Claims

1. A reset detection circuit for a logic circuit comprising: a first power supply line that supplies a first voltage; anda second power supply line that supplies a second voltage;a first determining means that operates with the first voltage and determines whether the second voltage is equal to or higher than a reset voltage for the logic circuit;a second determining means that operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining means; anda reset signal generating means that releases reset of the logic circuit when the first determining means determines that the second voltage is equal to or higher than the reset voltage for the logic circuit and at the same time the second determining means determines that the first voltage is equal to or higher than the minimum operating voltage, and outputs a reset signal for resetting the logic circuit when the first determining means determines that the second voltage is lower than the reset voltage for the logic circuit or the second determining means determines that the first voltage is lower than the minimum operating voltage.

2. The reset detection circuit of claim 1, wherein the first determining means includes: a voltage dividing circuit that divides the second voltage to a divided voltage; anda threshold circuit that compares the divided voltage of the voltage dividing circuit with a reference voltage corresponding to the reset voltage to determine whether the second voltage is equal to or higher than the reset voltage.

3. The reset detection circuit of claim 1, wherein the second determining means includes: a voltage dividing circuit that divides the first voltage to a divided voltage; anda threshold circuit that compares the divided voltage of the voltage dividing circuit with a reference voltage corresponding to a minimum operating voltage to determine whether the first voltage is equal to or higher than the minimum operating voltage.

4. The reset detection circuit of claim 1, wherein: the first determining means includes a first voltage dividing circuit that divides the second voltage to a first divided voltage, and a first threshold circuit that compares the first divided voltage of the first voltage dividing circuit with a first reference voltage corresponding to the reset voltage to determine whether the second voltage is equal to or higher than the reset voltage;the second determining means includes a second voltage dividing circuit that divides the first voltage to a second divided voltage, and a second threshold circuit that compares the second divided voltage of the second voltage dividing circuit with a second reference voltage corresponding to a minimum operating voltage to determine whether the first voltage is equal to or higher than the minimum operating voltage; andthe first reference voltage and the second reference voltage are equal to each other.

5. The reset detection circuit of claim 1, wherein: the reset voltage for the logic circuit is equal to a guarantee voltage for retaining a charge of a RAM; andthe logic circuit and the RAM are reset based on a determination of the first determining means as to whether the second voltage is equal to or higher than the reset voltage for the logic circuit.

6. The reset detection circuit of claim 1, further comprising: a third power supply line that supplies a third voltage; anda third determining means that operates with the first voltage and determines whether the third voltage is equal to or higher than a guarantee voltage for retaining a charge of a RAM,wherein the reset signal generating means releases the reset of the logic circuit when the first determining means determines that the second voltage is equal to or higher than the reset voltage for the logic circuit, the second determining means determines that the first voltage is equal to or higher than the minimum operating voltage, the third determining means determines that the third voltage is equal to or higher than the guarantee voltage for retaining the charge of the RAM, andwherein the reset signal generating means outputs the reset signal for resetting the logic circuit and the RAM when the first determining means determines that the second voltage is lower than the reset voltage of the logic circuit, the second determining means determines that the first voltage is lower than the minimum operating voltage, or the third determining means determines that the third voltage is lower than the guarantee voltage for retaining the charge of the RAM.

7. The reset detection circuit of claim 6, wherein the third determining means includes: a voltage dividing circuit for dividing the third voltage to a divided voltage; anda threshold circuit for comparing the divided voltage of the voltage dividing circuit with a reference voltage corresponding to the guarantee voltage for retaining the charge of the RAM to determine whether the third voltage is equal to or higher than the guarantee voltage for retaining the charge of the RAM.

8. The reset detection circuit of claim 6, wherein the third voltage is produced from the first voltage.

9. The reset detection circuit of claim 1, wherein the reset voltage is lower than the minimum operating voltage.

10. A semiconductor integrated circuit including the reset detection circuit of claim 1.