This disclosure relates generally to electric power generation, storage and distribution systems and methods. More particularly it pertains to improved frequency regulation in islanded microgrids.
As is known, contemporary electric power generation and distribution now include micro-grid architectures along with significant amounts of renewable energy sources. One advantage of a micro-grid is its ability to run in both grid connected and islanded mode of operation thereby providing higher flexibility and reliability. With increasing popularity of micro-grids and their existence becoming more prominent in existing power systems, more stringent adherence to frequency and voltage standards are important to maintain proper functionality of the electric grid. Accordingly, systems, methods and techniques that address any frequency and/or voltage violations in micro- grids would represent a welcome addition to the art.
An advance in the art is made according to aspects of the present disclosure directed to a resiliency controller for frequency regulation in islanded micro-grids.
In sharp contrast to the prior art, a frequency controller according to the present disclosure employs a dynamic droop algorithm for frequency control which advantageously results in improved down-time of the micro-grid such that greater economic benefit(s) from renewable energy sources may be realized.
A more complete understanding of the present disclosure may be realized by reference to the accompanying drawing in which:
The illustrative embodiments are described more fully by the Figures and detailed description. Embodiments according to this disclosure may, however, be embodied in various forms and are not limited to specific or illustrative embodiments described in the drawing and detailed description.
The following merely illustrates the principles of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope.
Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.
Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
Thus, for example, it will be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
The functions of the various elements shown in the Drawing, including any functional blocks labeled as “processors”, may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read-only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, may also be included.
Software modules, or simply modules which are implied to be software, may be represented herein as any combination of flowchart elements or other elements indicating performance of process steps and/or textual description. Such modules may be executed by hardware that is expressly or implicitly shown.
Unless otherwise explicitly specified herein, the FIGS. comprising the drawing are not drawn to scale.
Operationally, the energy management system provides active power dispatch reference control(s) for each distributed generator (DG) in the microgrid via communications interface 140 to the resiliency controller. Meanwhile, the resiliency controller collects measurement data from the microgrid via communications interface(s) 145. Based on the dispatch reference(s) and measurement data, the resiliency controller provides control signals to the distributed generators in the microgrid via the communications interface 140.
We note that the energy management system 130 controls the economic operation of the microgrid. Accordingly, by consideration of known energy management concepts of unit commitment, economic dispatch, renewable forecasting, etc., it determines and provides active power dispatch reference(s) to the reresiliency controller for each distributed generator of the microgrid.
With reference to the microgrid illustrated in
Notably, distributed generators in C1 and C2 are equipped with droop control in their local controllers. Note further that a DGs' output active power is related to the microgrid frequency, while a DGs' output reactive power is related to the microgrid voltage. Equations that may be used to describe these two relationships are as follows:
f
DG
=f*
DG
+k
f
_
DG(P*DG−PDG); and
V
DG
=V*
DG
+k
V
_
DG(Q*DG−QDG);
where fDG is the output frequency of the DG, f*DG is the reference frequency of the DG, kf_DG is the frequency droop coefficient, P*DG is the reference active power of the DG, and PDG is the output active power of the DG. Meanwhile, VDG is the output frequency of the DG, V*DG is the reference frequency of the DG, kV_DG is the frequency droop coefficient, Q*DG is the reference active power of the DG, and QDG is the output active power of the DG.
Note that distributed generators categorized in C3 (Renewables) are equipped with Maximum Power Point Tracking (MPPT) methods to harvest the maximum amount of energy under given weather conditions.
Turning now to
The dynamic droop control unit dispatches the amount of unbalanced power between the distributed generators and identifies the amount of power needed for each individual DG, from ΔPDG1 to ΔPDGn, which satisfies the following relationship:
ΔP=ΔPDG1+. . . +ΔPDGn.
Meanwhile, the active power references from the energy management system for each DG, from PEMS_DG1 to PEM_DGn are added together with ΔPDG1 to ΔPDGn respectively resulting in final active power references for each DG, from P*DG1 to P*DGn. Note also that the dynamic droop control unit determines the slope rates of droop curves for each DG namely, kf_DG1 to kf_DGn.The final active power references and slope rates of droop curves for each DG are sent to each DG from DG1 to DGn by way of the communications link.
With respect to the dynamic droop control unit shown in
Turning now to
As may be observed from simultaneous reference to
Alternatively, if SOC>95%, since again the ESS approaches full charge state, the DG in Category 2 will assume full responsibility for frequency control. In DG group Category 1, and DG group Category 2, the droop coefficients, kf_C1 and kf_C2, and the amount of shared unbalanced power, ΔPC1 and ΔPC2 are determined by the relationships shown in the blocks illustrated in
Alternatively, if 80%<SOC<=95%, the ESS has limited frequency control capability since its SOC is at high end. The frequency control responsibility is shared between the ESS and the DG in Category 2 to save certain amount(s) of fossil fuel. Based on the SOC value, in DG group Category 1 and DG group Category 2, the droop coefficients kf_C1 and kf_C2, and the amount of shared unbalanced power, ΔPC1 and ΔPC2 are determined by the relationships shown in the blocks shown in
Alternatively, if 10%<SOC<=20%, the ESS has limited frequency control capability since its SOC is at low end. The frequency control responsibility is shared between the ESS and the DG in Category 2 to save fossil fuel. Based on the SOC value, in DG group Category 1 and DG group Category 2 the droop coefficients the droop coefficients kf_C1 and kf_C2, and the amount of shared unbalanced power, ΔPC1 and ΔPC2 are determined by the relationships shown in the blocks shown in
Else, SOC is between 20% and 80%-which is a safe range. In this state, ESS takes the full responsibility for frequency control, and the fossil fuel consumption in DG group Category 2 can be minimized. The generators in DG group Category 2 can also be shut down to further reduce the fossil fuel consumption, if the amount of power from ESS and DG group Category 3 can support the load. In DG group Category 1 and DG group Category C2, the droop coefficients kf_C1 and kf_C2, and the amount of shared unbalanced power, ΔPC1 and ΔPC2 are determined by the relationships shown in the blocks illustrated in
Note that as shown in
Computer system 500 includes processor(s) 510, memory 520, storage device 530, and input/output structure 540. One or more busses 550 typically interconnect the components, 510, 520, 530, and 540. Processor 510 may be a single or multi core and. Additionally, the system may include multiple processors including multiple cores, accelerators etc. Still further, large scale systems of such multiple core, multi-processor systems 500 may be constructed to further enhance any parallelism desired.
Processor 510 executes instructions in which embodiments of the present disclosure may comprise steps described in one or more of the Drawing figures. Such instructions may be stored in memory 520 or storage device 530. Data and/or information may be received and output using one or more input/output devices.
Memory 520 may store data and may be a computer-readable medium, such as volatile or non-volatile memory. Storage device 530 may provide storage for system 500 including for example, the previously described methods. In various aspects, storage device 530 may be a flash memory device, a disk drive, an optical disk device, or a tape device employing magnetic, optical, or other recording technologies.
Input/output structures 540 may provide input/output operations to other systems/structures to which system 500 is communicatively coupled, including resiliency controller functional blocks, and or communication interfaces. Such systems may be included in any or all of the DGs employed as well.
At this point, while we have presented this disclosure using some specific examples, those skilled in the art will recognize that our teachings are not so limited. Accordingly, this disclosure should be only limited by the scope of the claims attached hereto.
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 62/309,988 filed Mar. 3, 2016 which is incorporated by reference as if set forth at length herein.
Number | Date | Country | |
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62309988 | Mar 2016 | US |