BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a layout view illustrating a structure of an exemplary thin film transistor array panel according to an exemplary embodiment,
FIGS. 2 and 3 are sectional views of the exemplary thin film transistor array panel of FIG. 1 taken along the lines II-II and II-II,
FIGS. 4, 7, 10, and 13 are layout views sequentially illustrating the manufacturing process of the exemplary thin film transistor array panel according to the exemplary embodiment of the present invention,
FIGS. 5 and 6 are sectional views of the exemplary thin film transistor array panel of FIG. 4 taken along the lines V-V and VI-VI,
FIGS. 8 and 9 are sectional views of the exemplary thin film transistor array panel of FIG. 7 taken along the lines VIII-VIII and IX-IX,
FIGS. 11 and 12 are sectional views of the exemplary thin film transistor array panel of FIG. 10 taken along the lines XI-XI and XII-XII, and
FIGS. 14 and 15 are sectional views of the exemplary thin film transistor array panel of FIG. 13 taken along the lines XIV-XIV and XV-XV.