This disclosure relates generally to clock distribution network architectures for digital devices with multiple clock networks and various clock frequencies such as microprocessors, application-specific integrated circuits (ASICs), and System-on-a-Chip (SOC) devices.
Resonant clock distribution networks have recently been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance.
Without the inductive elements of resonant clock distribution networks, conventional (i.e., non-resonant) clock distribution networks, rely almost exclusively on collections of buffers for distributing a reference clock signal to the multiple clocked elements, such as flip-flops and clock gaters, of a semiconductor device. In conventional clock distribution networks, the buffers are generally arranged in a topology that allows the reference clock signal to be supplied at a single root-point of the network and then propagated throughout the device through a sequence of buffer elements. The total propagation delays of the buffers along any given path from the root to some clocked element are generally balanced in some fashion, so that, for example, the clock signal arrives at all the various elements at approximately the same time. The propagation delays of individual buffers depend on a variety of factors, including the sizes of the transistors used to implement the buffers, the capacitive loads associated with the wiring used to interconnect the different buffers in the network, the temperature and voltage the buffers are operated at, and the specific characteristics of the various device materials that are actually realized during the manufacturing process.
The total propagation delay of the buffers along any given path from the root to some clocked element is also referred to as the insertion delay of the path, and the overall insertion delay profile of the overall clock network is one of the network's most important characteristics. The worst-case difference between the insertion delays of any two clocked elements in a semiconductor design is referred to as the clock skew between the devices. In general, increased clock skew is a hindrance to overall device performance, as large skews imply that new outputs of clocked-elements may become available later than anticipated, and inputs to clocked-elements may be needed earlier than anticipated, leading to an overall reduction in the amount of time that is available for the operation of the digital logic during each clock period.
As previously alluded to, variations in manufacturing parameters or operating conditions affect buffer propagation delays, and hence, the insertion delays of both paths and the overall clock distribution network. For example, process variations during manufacturing can result in faster or slower transistor switches, thus resulting in shorter or longer insertion delays, respectively. Furthermore, variations in the supply voltage or temperature during operation can affect insertion delays. To exacerbate the situation, these variations are “dynamic” in the sense that even a specific sample of a device will in the field be subject to voltages and temperatures that will vary from one instant to the next. These dynamic variations increase delay uncertainty, and subsequently reduce the level of performance that a device can be guaranteed to achieve under all anticipated operating conditions. In general, the magnitude of insertion delay variations is proportional to their target values. Therefore, clock distribution networks with relatively long insertion delays tend to have wider variations in their insertion delays than clock distribution networks with relatively short insertion delays.
In resonant clock distribution networks, insertion delays are typically in the order of a few tens of picoseconds, as these networks tend to have very low resistance, and tend to include only a few buffers. By contrast, conventional clock distribution networks typically include a large number of buffers and can exhibit insertion delays in the order of hundreds of picoseconds. Consequently, in the presence of variations in process parameters, voltage, and temperature, conventional clock distributions networks tend to have a relatively larger variation in insertion delay than resonant clock networks.
When resonant and conventional clock distribution networks are used in the same design, the difference in the insertion delays of the two networks can result in relatively large clock skews that can be detrimental to overall device performance. Typically, in such a design, it is possible to use automatic delay tuning blocks to compensate for the difference in the insertion delays of the two clock distribution networks, but due to the increased variability of advanced manufacturing processes, the range of insertion-delay mismatches can be significant, even to the point of being comparable to the longest insertion delays in the conventional clock distribution network. The overheads of automatic delay tuning blocks with such large tuning ranges can thus be significant, and even the design of a delay tuning block with such a large tuning range can be particularly challenging.
Another challenge with designs that include resonant and conventional clock distribution networks is the rate of variation in the clock skew between the two networks in the presence of dynamic variations during operation. Such variations may affect insertion delay within a clock cycle of operation. Moreover, their impact may vary significantly from cycle to cycle. Automatic delay tuning blocks are typically unable to react to such quick changes. Therefore, if the changes in the insertion delay of the resonant clock does not track the changes in the insertion delay of the conventional network, this difference is manifested as additional delay uncertainty that has a detrimental impact on overall device performance.
Architectures for resonant clock distribution networks have been described and empirically evaluated in the several articles, including: “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al., International Symposium on Low-Power Electronic Design, August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for Ultra_Low-Energy Applications,” by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004; “A 1.1 GHz Charge Recovery Logic,” by Sathe V., et al., International Solid-State Circuits Conference, February 2006; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al., IEEE 2006 Custom Integrated Circuits Conference, September 2006; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al., IEEE 2007 Custom Integrated Circuits Conference, September 2007; “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al., IEEE Journal of Solid State Circuits, Vol. 44, No. 1, January 2009. None of these articles describes any methods for using resonant and conventional clock distribution networks in the same design.
A design with resonant and conventional clock distribution networks was described in “A Resonant-Clock 200 MHz ARM926EJ-S Microcontroller,” by Ishii A., et al., European Solid-State Circuits Conference, September 2009. The design in that article used a programmable delay block to adjust the insertion delay of the reference clock that drives the resonant clock driver. That delay block was programmed by control signals external to the chip. Therefore, in that design, the resonant clock network was not capable of tracking the conventional clock distribution network in the presence of dynamic variations.
Methods for controlling the skew between a resonant clock network and a second clock network are described in US Pat. Appl. No. 20080150605 by Chueh J.-Y., et al. Those approaches rely on the use of digitally-controlled delay blocks to automatically adjust the delays of the reference clocks by monitoring the skew between clock signals in the two clock networks. This monitoring is performed over time using an integration function. It is thus unsuitable for providing quick adjustments on a cycle-by-cycle basis.
Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description.
A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
Disclosed herein is a clock distribution network, comprising: a conventional clock distribution network including a plurality of buffers configured to propagate a reference clock signal; a resonant clock distribution network including a resonant clock driver having a drive element electrically coupled to a clock node of the resonant clock driver, the drive element configured to receive and propagate a reference clock signal, a programmable delay electrically coupled between a reference clock input and the drive element; and a buffer network electrically coupled between the reference clock input to the resonant clock distribution network and the drive element of the resonant clock driver, wherein the buffer network mirrors a topology and loading of a sub-network of the conventional clock distribution network.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Other advantages and features will become apparent from the following description and claims. It should be understood that the description and specific examples are intended for purposes of illustration only and not intended to limit the scope of the present disclosure.
These and other objects, features and characteristics of the present invention will become more apparent to those skilled in the art from a study of the following detailed description in conjunction with the appended claims and drawings, all of which form a part of this specification. In the drawings:
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.
In the drawings, the same reference numbers and any acronyms identify elements or acts with the same or similar structure or functionality for ease of understanding and convenience.
Various examples of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. One skilled in the relevant art will understand, however, that the invention may be practiced without many of these details. Likewise, one skilled in the relevant art will also understand that the invention can include many other obvious features not described in detail herein. Additionally, some well-known structures or functions may not be shown or described in detail below, so as to avoid unnecessarily obscuring the relevant description.
A canonical resonant clock driver design is also shown in
The clock domain shown in
A possible approach to minimizing the difference between the insertion delays in the two clock distribution networks is to use a programmable delay block that adjusts the arrival time of the reference clock signal to the resonant clock driver. Such a block may be capable of tuning the delay of the reference clock automatically, by comparing the phases of clock edges at specific points in the two clock distribution networks. Alternatively, such a block may operate in response to external control signals. Such programmable delay blocks can be quite effective in compensating for manufacturing variations. In general, their effectiveness decreases significantly in the presence of dynamic variations that occur during operation, however, such as supply voltage and temperature variations, since such variations tend to have quite short time scales (e.g., from one cycle to the other), or they tend to be localized.
Programmable delay blocks also present a number of other challenges. Due to the significant difference in the insertion delays of resonant and conventional clock distribution networks, the variation in the clock skew between the two networks due to supply voltage and temperature variations can be large. Designing programmable delay blocks that can compensate for a large range of clock skews is a challenging task. Moreover, the energy consumption and area requirements of such blocks tend to be proportional to the range of clock skews they need to support. Consequently, such blocks tend to have relatively high energy consumption and area overheads.
While
As in the programmable delay block architecture shown in
The architecture described herein is generally applicable to resonant clock networks that use alternative embodiments of the resonant clock driver shown in
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense (i.e., to say, in the sense of “including, but not limited to”), as opposed to an exclusive or exhaustive sense. As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements. Such a coupling or connection between the elements can be physical, logical, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
The above Detailed Description of examples of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific examples for the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. While processes or blocks are presented in a given order in this application, alternative implementations may perform routines having steps performed in a different order, or employ systems having blocks in a different order. Some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified to provide alternative or sub-combinations. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed or implemented in parallel, or may be performed at different times. Further any specific numbers noted herein are only examples. It is understood that alternative implementations may employ differing values or ranges.
The various illustrations and teachings provided herein can also be applied to systems other than the system described above. The elements and acts of the various examples described above can be combined to provide further implementations of the invention.
Any patents and applications and other references noted above, including any that may be listed in accompanying filing papers, are incorporated herein by reference. Aspects of the invention can be modified, if necessary, to employ the systems, functions, and concepts included in such references to provide further implementations of the invention.
These and other changes can be made to the invention in light of the above Detailed Description. While the above description describes certain examples of the invention, and describes the best mode contemplated, no matter how detailed the above appears in text, the invention can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the invention disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the invention with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the invention under the claims.
While certain aspects of the invention are presented below in certain claim forms, the applicant contemplates the various aspects of the invention in any number of claim forms. For example, while only one aspect of the invention is recited as a means-plus-function claim under 35 U.S.C. §112, sixth paragraph, other aspects may likewise be embodied as a means-plus-function claim, or in other forms, such as being embodied in a computer-readable medium. (Any claims intended to be treated under 35 U.S.C. §112, ¶6 will begin with the words “means for.”) Accordingly, the applicant reserves the right to
add additional claims after filing the application to pursue such additional claim forms for other aspects of the invention.
This patent application is a conversion of and claims priority to U.S. Provisional Patent Application No. 61/250,830, entitled SYSTEMS AND METHODS FOR RESONANT CLOCKING INTEGRATED CIRCUITS, filed Oct. 12, 2009, which is incorporated herein in its entirety. This patent application is related to the technologies described in the following patents and applications, all of which are incorporated herein in their entireties: U.S. patent application Ser. No. 12/125,009, entitled RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WITH MULTIPLE CLOCK NETWORKS, filed Oct. 12, 2009, which claims priority to U.S. Provisional Patent Application No. 60/931,582, entitled RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR PROGRAMMABLE LOGIC DEVICES, filed May 23, 2007;U.S. patent application Ser. No. 12/903,154, entitled RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE DRIVERS, filed Oct. 12, 2010;U.S. patent application Ser. No. 12/903,158, entitled ARCHITECTURE FOR CONTROLLING CLOCK CHARACTERISTICS, filed Oct. 12, 2010;U.S. patent application Ser. No. 12/903,163, entitled METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTION NETWORKS WITH NO INDUCTOR OVERHEAD, filed Oct. 12, 2010;U.S. patent application Ser. No. 12/903,166, entitled ARCHITECTURE FOR ADJUSTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTION NETWORKS, filed Oct. 12, 2010;U.S. patent application Ser. No. 12/903,168, entitled ARCHITECTURE FOR FREQUENCY-SCALED OPERATION IN RESONANT CLOCK DISTRIBUTION NETWORKS, filed Oct. 12, 2010;U.S. patent application Ser. No. 12/903,172, entitled ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NETWORKS, filed Oct. 12, 2010;U.S. patent application Ser. No. 12/903,174, entitled ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NETWORKS, filed Oct. 12, 2010; and
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