BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to control methods used in resonant converters. More particularly, the present invention relates to individual converter control and paralleled resonant converters with active current-sharing control.
2. Description of the Prior Art
Generally, a resonant converter uses a resonant-tank circuit to shape switch voltages or current waveforms, or both, to minimize switching losses and to allow high-frequency operations without compromising conversion efficiency. Resonant converters are therefore extensively used in state-of-the-art power supplies that offer the highest power densities and efficiencies. Resonant converters are also preferred as power supply circuits for medical applications because of their superior electromagnetic interference (EMI) performance relative to their “hard”-switched counterparts. As resonant converters absorb component parasitics into their resonant-tank circuit (e.g., output capacitance of semiconductor switches, leakage or magnetizing inductance of transformers, or any combination thereof), resonant converters are used in applications where the parasitics are pronounced, such as high-voltage power supply circuits and contactless or inductive power transfer applications.
FIGS. 1(
a) and 1(b) show two typical topologies for isolated resonant power converters. FIG. 1(a) shows a half-bridge topology, in which the resonant tank circuit includes inductor LR and capacitors CR1 and CR2. FIG. 1(b) shows a full-bridge topology, in which the resonant tank circuit includes inductor LR and capacitor CR. Because in both resonant tank circuits the resonant inductor is connected in series with the resonant capacitor or capacitors, the circuits of FIGS. 1(a) and (b) are series-resonant converters. If the magnetizing inductance of transformer TR is relatively small (e.g., only several times the inductance of resonant inductor LR), the converters operate as LLC series-resonant converters. To maximize conversion efficiency in applications with relatively low output voltages (e.g., 60 volts or less), secondary-side diode rectifiers are usually provided by synchronous rectifiers. In FIGS. 1(a) and 1(b), the synchronous rectifiers are implemented by low on-resistance metal-oxide-semiconductor field effect transistors (“MOSFETs”). Using MOSFETs as synchronous rectifiers also makes the resulting converter bidirectional because controllable switches on both the primary side and the secondary side of the transformer allow power to flow in both directions. The secondary side of an isolated resonant converter can be implemented by a single secondary winding and a full-wave rectifier, rather than the center-tapped secondary winding shown in FIGS. 1(a) and (b).
Generally, a resonant converter operates with variable switching-frequency control. When operating above the resonant frequency, a resonant converter operates with zero voltage-switching (ZVS) in the primary switches. Alternatively, when operating below the resonant frequency, a resonant converter operates with zero current-switching (ZCS). The article “Resonant, Quasi-Resonant, Multi-Resonant, and Soft-Switching Techniques—Merits and Limitations,” by M. M. Jovanović, published in the International Journal of Electronics, Vol. 77, no. 5, pp. 537-554, November 1994, discloses in detail resonant converter topologies and control.
FIG. 1(
c) shows waveforms of switch-control signals for ZVS operation in series-resonant converters, such as those shown in FIGS. 1(a) and (b). As shown in FIG. 1(c), each switch operating with a 50% duty ratio, with the primary switches of the same leg (i.e., switches SP1 and SP2, or Sp3 and SP4) operate in a substantially complementary (i.e., non-overlapping) fashion to avoid cross-conduction. A feedback control loop providing output regulation determines the frequency of primary switch operations. On the secondary side, the synchronous rectifier switches are synchronized to switch at the zero crossings of the resonant current. Specifically, synchronous rectifier SS1 is synchronized to turn on at the moment resonant current iP changes from negative to positive and turn off at the moment resonant current iP changes from positive to negative, while synchronous rectifier SS2 is synchronized to turn on at the moment resonant current iP changes from positive to negative and turn off at the moment resonant current iP changes from negative to positive, as illustrated in FIG. 1(c). To achieve ZVS in a practical implementation, the duty ratio of each primary switch is set to a value that is slightly less than 50% by introducing a short delay between the turning-off and the turning-on of its complementary switch in the same leg. During this dead time (i.e., when neither complementary switch is closed), the current is commutated from the switch that is being turned off to the anti-parallel diode in the complementary switch, so as to create a condition for the complementary switch's subsequent ZVS turning on. Typically, each secondary-side synchronous rectifier of the resonant converter is also operated with a duty ratio that is slightly less than 50%.
Variable switching-frequency control is generally seen as a drawback of a resonant converter, especially in an application with a wide input voltage range or a wide output voltage range. Specifically, as the input or output voltage range increases, the control frequency range also increases, so that driving and magnetic component losses also increase, thereby reducing conversion efficiency. Furthermore, in many applications, the converter is restricted to operate within a relatively limited frequency range to avoid interfering with other parts of the system. While a resonant converter can operate with a constant frequency (i.e., in a “clamp-mode” operation), such an operation is not desirable because the increased circulating energy in the resonant tank circuit significantly degrades conversion efficiency.
In a series-resonant converter, such as that shown in FIG. 1(a) or FIG. 1(b), the output voltage ripple is determined by the AC-component of the secondary-side rectified resonant current flowing through output capacitor CO. Such a converter is more suited for a relatively low output current operation. To achieve a low output-voltage ripple in a high-current application, a lager output capacitor is required. The output capacitor is typically implemented by parallel electrolytic capacitors or ceramic capacitors. For converter applications that require a relatively long life time (e.g., an automotive on-board charger, an automotive DC/DC converter, a solar inverter, or an LED driver), it is not desirable to use electrolytic capacitors.
The output capacitor can be significantly reduced by interleaving—i.e., by operating multiple converters in parallel and providing a phase shift between the gate-drive signals. Interleaving substantially cancels the current ripples at the input and output. By interleaving, a resonant converter with a relatively small C-type output capacitor (e.g., the resonant converters of FIGS. 1(a) and (b)) can be used in a high output current application. However, interleaving variable frequency-controlled resonant converters requires that the switching frequencies be synchronized (i.e., the parallel converters operate at the same variable frequency). However, because of the inevitable mismatch between the resonant tank components, the interleaved resonant converters would not equally share a load current (or power) even with identical input and output voltages and switching frequency. Therefore, when mismatched components are present, additional control means (i.e., a control mechanism that is independent of the switching-frequency control) is required to achieve an acceptable current sharing among the interleaved resonant converters.
U.S. Patent Application Publication 2012/0153730, entitled “Interleaved LLC Converter Employing Active Balancing,” discloses a control method for interleaving LLC converters with active current balancing. Under that control method, the input terminals of each interleaved converter is connected to a separate DC power source and the power source voltages (i.e., the input voltages of the LLC converters) are controlled to achieve and to maintain current balance between the interleaved converters. Such a method cannot be applied in an application where the input voltages of the LLC converters are not controllable or if only one DC power source is available.
SUMMARY
The present invention provides control methods for resonant converters that offer improved performance. Specifically, the control methods of the present invention provide improved performance in resonant converters that operate with a wide input-voltage range or a wide output-voltage range (or both) by substantially reducing the switching-frequency range. Reduction in the switching frequency range is achieved by controlling the output voltage with a combination of variable-frequency control and time-delay control. According to one embodiment of the present invention, variable-frequency control may be used to control the primary switches of an isolated resonant converter, while delay-time control may be used to control secondary-side rectifier switches provided in place of diode rectifiers. The secondary-side control may be implemented by sensing the secondary current or the primary current (or both) and by delaying the turn ing-off of the corresponding secondary switch with respect to the zero crossings in the secondary current or the primary current. Generally, the delay time is responsive to the input voltage, the output voltage, or both. According to one embodiment of the present invention, the primary and secondary switches operate with substantially the same switching frequency and each having a duty ratio of approximately 50%. To achieve ZVS operation, a short dead time is introduced between the turning-off instant of a primary switch and the corresponding turning-on instant in the complementary primary switch.
According to one embodiment of the present invention, a control method provides active current-sharing control between paralleled resonant converters, including interleaved resonant converters. The load current of each paralleled converter is directly or indirectly sensed from the secondary current, the primary current or both. The current difference between the sensed current value and a desired reference current is used to adjust the delay time of each paralleled converter, so that the sensed currents of the paralleled converters are substantially equal. This current-sharing delay-time control supplements the delay-time control that is responsive to the input or output voltage (or both).
The control methods of the present invention are applicable to both isolated and non-isolated series-resonant converters. In non-isolated converters, time-delay control is derived from sensing the zero crossings of one or more resonant tank currents and from delaying the turning-off of the corresponding rectifier switch for an amount of time based on the input voltage or the output voltage (or both).
The present invention is better understood upon consideration of the following detailed description and accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(
a) and 1(b) show a half-bridge topology and a full-bridge topology, respectively, for typical isolated resonant power converters.
FIG. 1(
c) shows timing diagrams of switch-control signals for ZVS operation in series-resonant converters, such as those shown in FIGS. 1(a) and (b).
FIG. 2 illustrates a control method in isolated half-bridge series-resonant converter 200 with a center-tap secondary winding in transformer TR, according to one exemplary embodiment of the present invention.
FIG. 3 shows waveforms of primary switches SP1 and SP2, secondary switches SS1 and SS2, and primary current IP in half-bridge resonant converter 200 of FIG. 2, according to one embodiment of the present invention.
FIG. 4 shows half-bridge resonant converter 400 with a full-wave secondary-side rectifier and which uses secondary-current sensing, in accordance with one embodiment of the present invention.
FIG. 5 shows waveforms of primary switches SP1 and SP2, secondary switches SS1, SS2, SS3, and SS4, and secondary current IS in full-bridge resonant converter 400 of FIG. 4, according to one embodiment of the present invention.
FIGS. 6(
a) and 6(b) show half-bridge series-resonant converters with full-wave secondary-side rectifier implemented by two low-side switches and by two switches in totem-pole configuration, respectively, controlled in accordance with the present invention.
FIG. 7 shows a half-bridge resonant converter with a voltage doubler rectifier, controlled according to one embodiment of the present invention.
FIG. 8 shows a full-bridge series-resonant converter with a full-wave secondary-side rectifier, controlled according to one embodiment of the present invention.
FIG. 9 shows full-bridge non-isolated resonant converter 900 with a full-wave rectifier, controlled according to one embodiment of the present invention.
FIG. 10 shows a symmetrical bidirectional half-bridge resonant converter, controlled according to one embodiment of the present invention.
FIG. 11 shows two series-resonant converters connected between common input voltage source VIN and a common output load, controlled according to one embodiment of the present invention.
FIG. 12 shows waveforms of (i) primary switches SP11 and SP21, secondary switches SS11 and SS21, and secondary current IS1 in resonant converter 1150a of FIG. 11, and (ii) primary switches SP12 and SP22, secondary switches SS12 and SS22, and secondary current IS2 in resonant converter 1150b of FIG. 11, according to one embodiment of the present invention.
FIG. 13 shows delay-time control to allow active load current-sharing between interleaved converters, in accordance with a second embodiment of the present invention.
FIG. 14 shows delay-time control in interleaved converters 1450a and 1450b with wide input voltage range or wide output voltage range (or both) that achieves simultaneously both active current-sharing control and frequency-range reduction, in accordance with one embodiment of the present invention.
FIG. 15 shows active current-sharing control for interleaved converters 1550a and 1550b having independent input sources, in accordance with one embodiment of the present invention.
FIG. 16 shows active current-sharing control for interleaved converters 1650a and 1650b supplied by stacked input sources, in accordance with one embodiment of the present invention.
Like elements in the figures are assigned like reference numerals.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 2 illustrates a control method in isolated half-bridge series-resonant converter 200 with a center-tap secondary winding in transformer TR, according to one exemplary embodiment of the present invention. (Except for its control circuit, half-bridge series resonant converter 200 has the same topology as the half-bridge resonant converter of FIG. 1(a)). As shown in FIG. 2, the half-bridge series-resonant converter 200 uses an isolation transformer TR with a center-tapped secondary winding. The primary side of the converter includes switches SP1 and SP2, resonant capacitors CR1 and CR2, and resonant inductor LR. The secondary side of the resonant converter includes switches SS1 and SS2 and output or filter capacitor CO, which is coupled across the load. Alternatively, filter capacitor CO may be coupled to the load through a second-stage LC filter. Even when present, the second-stage LC filter does not substantively affect the control method of the present invention. Accordingly, the second-stage LC filter is not included in this detailed description to simplify the figure and its related descriptions.
As illustrated in FIG. 2, output voltage regulation is achieved using a combination of variable-frequency control and time-delay control. Specifically, variable-frequency control is applied to primary switches SP1 and SP2, and delay-time control is applied to secondary-side switches SS1 and SS2. FIG. 3 shows waveforms of primary switches SP1 and SP2, secondary switches SS1 and SS2, and primary current IP in half-bridge resonant converter 200 of FIG. 2, according to one embodiment of the present invention. As shown in FIG. 3, waveforms for switches SP1, SP2, SS1, and SS2 show that these switches all operate with the same switching frequency, each having a duty cycle of approximately 50%.
Controller 250 receives output voltage VO, which is scaled by the sensing and scaling circuit 201 to provide scaled voltage VO(scld). Error signal VE is generated by subtracting a reference output voltage (voltage VO(REF)) from scaled voltage VO(scld). From error signal VE, compensated error amplifier 202 provides amplified error signal VEA, which sets frequency fS for voltage-controlled oscillator (VCO) 203. VCO 203, in turn, regulates primary switches SP1 and SP2 at switching frequency fS. To achieve zero-voltage switching in the complementary primary switches of the same leg (e.g., primary switches SP1 and SP2), a small dead time is provided between the turning-on instants and the turning-off instants of these complementary switches.
Controller 250 provides delay-time control to secondary switches SS1 and SS2 based on sensed primary current IP in transformer TR. As shown in FIG. 3, controller 250 delays the turning-off of the corresponding secondary switches relative to the zero crossings in primary current IP. The delay time is determined by delay time control circuit 207 based on zero crossings of primary current IP detected in zero-current detector (ZCD) 206, and one or both of scaled output voltage VO(scld) and scaled input voltage VO(scld). Delay-time control reduces the control frequency range of the resonant converter in an application with a wide input voltage range or a wide output voltage range. In an application with a substantially constant output voltage and a wide input voltage range, the delay time is responsive only to the input voltage range. Similarly, in an application with a substantially constant input voltage and a wide output voltage range, the delay-time is responsive only to the output voltage range (i.e., sensing of the input voltage is unnecessary).
ZCD 206 senses and scales received primary current IP. Alternatively, instead of sensing primary current IP, delay-time control according to the present invention may also be achieved by sensing one or more secondary currents. Where the magnetizing inductance of the transformer (measured on the primary side) is relatively high, such that the contribution of the magnetizing current to the primary current is negligible, the zero crossings in both the secondary current and the primary current occur substantially simultaneously (as iS=n×iP). In that case, delay-time control performance is not affected by whether the primary current or the second current is sensed. The selection of which current to sense may be made based on such consideration as ease of sensing or cost. With a center-tap transformer, sensing the primary current is typically preferred because it requires less components. Also, sensing on the low current side is preferred over sensing on the high current side because of a lesser current-sensing loss. However, for a smaller magnetizing inductance, such as in series-resonant LLC converters, the delay-time control range may be affected by the choice of which side the current is sensed. Specifically, where magnetizing current iM is a non-negligible part of the primary resonant current, zero-crossings in the primary current and the secondary current are phase shifted relative to each other, as iS=n(iP−iM), so that the zero-crossings in the secondary current occur when iP=iM, i.e., for a non-zero primary current. The zero-crossings in the primary current are delayed by the time interval between the zero-crossing in the secondary current and the secondary current whereby the value iS=−n×iM is reached. Because in each cycle a zero-crossing in the secondary current occurs before a zero-crossing in the primary current, delay-time control based on primary-current sensing provides a delay time that is at least equal to the time difference between the zero-crossings of the primary current and the secondary current. With secondary-side sensing, the delay-time control can set the delay time all the way down to zero.
As delay-time control increases the energy in the resonant tank circuit and makes the converter exhibit a boost characteristic, the control-frequency range is also reduced. Specifically, when the resonant converter of FIG. 1(a) is operated without delay-time control (i.e., with the control timing scheme of FIG. 1(c)), the voltage across resonant inductor LR is given by the difference between one-half of input voltage VIN and the primary-winding voltage (which is the reflected output voltage nVO, for a transformer with a turns ratio of n). Therefore, during the time interval when primary switch Sp, and secondary switch SS, are both conducting and primary current iP is positive, the voltage across resonant inductor LR (which increases the inductor current and, therefore, its energy) is 0.5VIN-nVO. However, when delay-time-control is applied according to FIG. 3 to the secondary-side switches SS, and SS2, the resonant-inductor voltage across inductor LR during interval [TO-T1] is 0.5VIN+nVO, because output voltage VO is connected to the resonant tank circuit with opposite polarity, as positive primary current iP induces a secondary current to flow through closed switch SS2 and output capacitor CO. With delay-time control applied to the secondary switches, a higher voltage is achieved across resonant inductor LR (hence, a higher amount of energy is stored in resonant inductor LR). Therefore, under the same input voltage and switching frequency, secondary-side delay-time control provides a higher output voltage that is proportional to the delay time (i.e., the time when the secondary winding is connected to output voltage VO with opposite polarity). This boost characteristic makes optimizing circuit performance possible by selecting (i) a higher turns ratio in the transformer to reduce primary conduction losses and (ii) a higher magnetizing inductance to reduce circulating (i.e., magnetizing) current loss. Because of this boost characteristic, delay-time control according to the present invention is favored when operating in a low input voltage range or in a high output voltage range. Specifically, the maximum delay time, which is approximately TS/4, where TS is the switching period, is set at the minimum input voltage or the maximum output voltage. This delay time is progressively reduced for higher input voltage or lower output voltage. (Therefore, delay-time control is typically not used at the middle and high input voltages, or nominal and low output voltages.) The control methods of the present invention may be implemented by either analog circuitry, digital control circuitry, or a combination of both. A microcontroller- or DSP-based implementation is preferred, as the delay time depends on input or output voltages, which are easily programmable.
The control methods of the present invention are applicable to converters of any series-resonant topology. FIG. 4 shows half-bridge resonant converter 400 with a full-wave secondary-side rectifier and which uses secondary-current sensing, in accordance with one embodiment of the present invention. FIG. 5 shows waveforms of primary switches SP1 and SP2, secondary switches SS1, SS2, SS3, and SS4, and secondary current IS in resonant converter 400 of FIG. 4, according to one embodiment of the present invention. As shown in FIG. 5, secondary switches SS2 and SS3 are both conducting during delay-time intervals [TO-T1] and [T3-T4] to improve efficiency (i.e., thereby reducing the conduction times in the body diodes of secondary switches SS2 and SS3 when both switches carry negative currents). The voltage across resonant inductor LR during intervals [TO-T1] and [T3-T4] is 0.5VIN because the secondary winding is effectively shorted, as positive primary current iP induces a secondary current to flow through closed switches SS2 and SS3. With delay-time control applied to the secondary switches, a higher voltage is achieved across resonant inductor LR than that without delay-time control.
In FIG. 5, switches in the same leg of the full-bridge operate in a substantially complementary fashion. To achieve switching under zero voltage condition in the complementary primary and secondary switches, a small dead time is provided between the turning-on and turning-off instants in these complementary switches.
FIGS. 6(
a) and 6(b) illustrate examples of resonant converters that implement full-wave secondary-side rectifiers using two controllable switches. In addition to being applicable to resonant converters of FIGS. 6(a) and 6(b), the methods of the present invention are also applicable to (i) a half-bridge resonant converter with a voltage doubler rectifier, as shown in FIG. 7, and (ii) a full-bridge resonant converter with a full-wave rectifier, as shown in FIG. 8. In the converter of FIG. 8, diagonal primary switches SP1 and SP3 (and, likewise, diagonal primary switches SP2 and SP4) are simultaneously turned on and off, while secondary switches SS1-SS4 are operated according to the waveforms of secondary switches SS1-SS4 of FIG. 5.
The control methods of the present invention are also applicable to resonant converters that inductively transfer energy over a large distance between separated primary winding (transmitter) and secondary winding (receiver) of the transformer. In these embodiments with wireless power transfer, the output voltage, current, or power that is measured on the secondary side of the transformer may be transmitted over a high-frequency wireless communication network to the primary side of the transformer to regulate the amount of transferred inductive energy.
The control methods of the present invention are also applicable to non-isolated series-resonant converters, such as resonant converter 900 of FIG. 9. FIG. 9 shows full-bridge non-isolated resonant converter 900 with a full-wave rectifier, controlled according to one embodiment of the present invention. In non-isolated converter 900 of FIG. 9, time-delay control is implemented by (i) sensing the zero crossings of the resonant-tank current, and (ii) delaying the turning-on of the corresponding rectifier switch by an amount of time based on the input voltage, the output voltage, or both.
Resonant converters with secondary-side switches controlled according to the methods of the present invention are inherently bidirectional (i.e., such converters are capable of transferring power in either direction). In some isolated converters, bidirectional power control may require sensing of currents on both sides of the transformer. In addition, for some isolated topologies, additional control for flux-balancing in the transformer core may be necessary. FIG. 10 shows a symmetrical bidirectional half-bridge resonant converter to which the methods of the present invention are applicable. The waveforms for the switch control signals in the converter of FIG. 10 according to the present invention are the same for either power flow direction. Specifically, upon identification of the power flow direction, the control signals for the appropriately identified primary and secondary switches may be applied and the current from the appropriately identified side of the transformer may be sensed according to the waveforms shown in FIG. 3.
The delay-time control of the present invention may also be used to control active load current-sharing in paralleled or interleaved resonant converters, i.e., to make and to maintain the output currents of paralleled or interleaved resonant converters to be substantially balanced. FIG. 11 shows series-resonant converters 1150a and 1150b connected between common input voltage source VIN and a common output load. Conventional variable-frequency feedback control may be used to regulate the output voltage. As shown in FIG. 11, paralleled converters 1150a and 1150b operate with the same switching frequency fS, which is set by output-voltage controller 1151 that includes output-voltage error amplifier with compensation circuit 1101 and VCO 1102. Frequency fS at VCO 1102 is determined by output-voltage error amplifier with compensation circuit 1101 based on a voltage difference between scaled sensed output voltage VO(scld) and reference voltage VREF. Interleaving is implemented by offsetting the waveforms of the control signals in the corresponding primary switches of the two converters by about 90° (e.g., by about one-quarter of the switching period TS/4), as shown in FIG. 12. FIG. 12 shows waveforms of (i) primary switches SP11 and SP21, secondary switches SS11 and SS21, and secondary current IS, in resonant converter 1150a of FIG. 11, and (ii) primary switches SP12 and SP22, secondary switches SS12 and SS22, and secondary current IS2 in resonant converter 1150b of FIG. 11, according to one embodiment of the present invention.
In the interleaved resonant converters of FIG. 11, both the secondary current and the output current are sensed in each resonant converter. The output current of each converter is compared with current reference IREF that corresponds to ideal current sharing (i.e., one-half of load current IO, or IREF=IO/2). For each converter, the difference or “error” between the actual output current and current reference IREF is processed by the corresponding current sharing error amplifier with compensation circuit (i.e., circuit 1104a or 1104b). In each converter, the result sets in delay time control circuits 1105a and 1105b the delay times of the respective secondary switches relative to the corresponding secondary-current zero crossings. Since the typical current mismatch between parallel converters is relatively small, the delay times required for current balancing are also relatively short. Scaling, filtering, and other conditioning of the individual sensed output currents that may be required are performed in the respective current sharing error amplifier with compensation circuits (i.e., circuit 1104a and circuit 1104b). If the sensed output currents are scaled, the current reference in each converter also needs to be appropriately scaled. Alternatively, instead of sensing the output current, active current sharing control according to the present invention may also sense another current that is proportional to the output current. Examples of such an alternative current to be sensed include a rectified secondary current, the secondary current, or the primary current. The accuracy of controlling current-sharing may be affected, however, by the choice of sensing current. Generally, sensing the output current indirectly reduces control accuracy.
FIG. 13 shows delay-time control to allow active load current-sharing between paralleled converters 1350a and 1350b, in accordance with a second embodiment of the present invention. As shown in FIG. 13, the output currents of the paralleled converters 1350a and 1350b are not sensed directly. Instead, the output currents are obtained indirectly from sensed secondary currents iS1 and iS2. In FIG. 13, secondary currents iS1 and iS2 are rectified and filtered to provide rectified currents <|iS1|> and <|iS2|>, which are proportional to corresponding output currents. The difference between rectified currents <|iS1|> and <|iS2|> are processed by the respective current-sharing error amplifier with compensation circuits 1304a and 1304b. Each current-sharing error amplifier with compensation circuit sets the delay time for the corresponding secondary switches relative to the secondary current zero crossings.
FIG. 14 shows delay-time control in parallel converters 1450a and 1450b with wide input voltage range or wide output voltage range (or both) that achieves simultaneously both active current-sharing control and frequency-range reduction, in accordance with one embodiment of the present invention. As shown in FIG. 14, in addition to active current-sharing control, delay-time control may be used to reduce the frequency range of two interleaved converters 1450a and 1450b with a wide input voltage range. Frequency range reduction is achieved by making the delay time responsive to both the input voltage and the output current of each paralleled converter. In the exemplary embodiment of FIG. 14, current-sharing control is implemented by processing a difference between sensed rectified output currents iO1 and iO2 The difference between rectified output currents iO1 and iO2 are taken after each current has been low-pass filtered to extract their respective average values.
Active current-sharing control of the present invention may be implemented in multiple converters having output terminals connected in parallel and input voltages supplied from different voltage sources, as shown in the exemplary embodiments of FIGS. 15 and 16. FIG. 15 shows active current-sharing control for converters 1550a and 1550b having independent input sources, in accordance with one embodiment of the present invention. FIG. 16 shows active current-sharing control for converters 1650a and 1650b supplied by stacked input sources, in accordance with one embodiment of the present invention.
Stacked input sources VIN1 and VIN2 of FIG. 16 may be, for example, serially connected capacitors that are coupled to a common input source VIN. The delay-time control method of the present invention may be used to balance the voltages across these capacitors. In this input-capacitor voltage balancing control, the two converters regulate the output voltage by frequency control, while each converter regulates its input voltage across the corresponding input capacitor. Output voltage regulation may be achieved using an error difference between output voltage VO and desired reference voltage VREF(OUT). In addition, the error difference may also be used to adjust the switching frequency for the two converters. Interleaving is implemented by offsetting the waveforms of the control signals in the corresponding primary switches of the two converters by about 90°. The input capacitor voltage is regulated by processing an error difference between the input capacitor voltage and desired reference voltage VREF(IN) derived from sensing the input voltage via a sensing and scaling network. The error difference determines a delay time adjusted to a value necessary to achieve and maintain the desired input voltage. By selecting reference voltage VREF(IN) to be VIN/2 (e.g., from a voltage divider formed by equal resistors), converters 1650a and 1650b can achieve perfectly balanced input voltages.
Stacked input sources may be serially connected multiple capacitors that are coupled to a common input source VIN. The delay-time control method of the present invention may be used to balance the voltages across these capacitors. The converters regulate the output voltage by frequency control with interleaving operation, while each converter regulates its input voltage across the corresponding input capacitor.
The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of this invention are possible. The present invention is set forth in the following claims.
Patent Application
20150229225
