Claims
- 1. A method comprising:
testing a computer system using a plurality of test units, each test unit being associated with its respective core function circuitry both located in a separate one of a plurality of primary components of the computer system, the plurality of test units to communicate with one another to determine whether a specification of the computer system is satisfied, without requiring a processor core of the computer system to execute an operating system program for the computer system.
- 2. The method of claim 1 wherein the plurality of test units determine whether a memory subsystem of the computer system and an I/O subsystem of the computer system satisfy a specification, without requiring the processor core to execute the operating system program.
- 3. The method of claim 1 wherein the computer system is tested with said plurality of primary components installed on a motherboard of the computer system which has not yet been assembled into a platform, prior to said tested motherboard being shipped to a platform assembly entity.
- 4. The method of claim 1 wherein the computer system is tested with said plurality of primary components installed on a motherboard of the computer system that has been assembled into a platform, prior to said assembled platform being shipped to an end user.
- 5. A method comprising:
testing a computer system using electrical stimuli that are under control of a plurality of test units located in a processor package, a chipset package, and memory subsystem hardware that make up the computer system, the test units to evaluate the computer system, without requiring a processor core of the processor package to execute an operating system program for the computer system, to determine whether specified requirements of a parallel, component interconnect bus intended for operation above 500 MHz bus clock frequency, are satisfied.
- 6. The method of claim 5 wherein one of the test units is located on-chip with the processor core in the processor package and further issues bus transactions to determine whether an I/O subsystem of the computer system meets a specification, without requiring the processor core to execute the operating system program.
- 7. The method of claim 5 wherein each test unit has a built-in pattern generator and automatically takes control of I/O buffer circuitry of its IC package upon power being applied and then conducts a test of an interconnect or issues transactions to test an I/O subsystem, without requiring any program to be executed by the system to configure the test unit and start said test.
- 8. The method of claim 5 further comprising:
conducting integrated circuit design validation, under the direction of the test unit, of said one of the processor package, chipset package, and memory subsystem hardware in which the test unit is located.
- 9. A computer system comprising:
a printed wiring board having a component interconnect; and a plurality of primary integrated circuit (IC) components including a processor and memory each having its respective core function circuitry, built-in test unit, and I/O buffer circuitry, the plurality of IC components being installed on the board with the respective I/O buffer circuitry being coupled to the component interconnect, the built-in test units to conduct test stimulus and capture through the I/O buffers and the component interconnect, at normal operation bus clock frequency, to cover a fault spectrum of the computer system.
- 10. The system of claim 9 wherein the memory has a memory core, the built-in test unit of the memory is to further conduct a test stimulus and capture of the memory core.
- 11. The system of claim 9 wherein the fault spectrum of the computer system includes fault spectrums of the component interconnect, the memory, and an I/O subsystem of the computer system.
- 12. The system of claim 9 wherein the test unit that is in the processor is to conduct at speed bus transactions through the I/O buffer circuitry to test an I/O subsystem of the computer system.
- 13. The system of claim 9 further comprising:
a platform management subsystem installed on the board and coupled to the built-in test units via a separate bus than the component interconnect, the subsystem to execute firmware for configuring the test units with a test pattern.
- 14. The system of claim 13 wherein the firmware is to be executed prior to booting an operating system program of the computer system.
- 15. The system of claim 9 wherein each test unit includes an interconnect test cell and a transaction test cell, the interconnect test cells to conduct test stimulus and capture independent of a bus protocol so that the interconnect is stressed, and the transaction test cell to conduct test stimulus and capture in accordance with a bus protocol for the interconnect.
- 16. The system of claim 15 wherein the plurality of primary components further include a chipset, a transaction test cell of the chipset is to conduct test stimulus and capture at a transaction layer for testing an I/O subsystem of the computer system.
- 17. An article of manufacture comprising:
an integrated circuit (IC) die having core function circuitry that is to be part of a primary component of a computer system, the core function circuitry being coupled to on-chip I/O buffer circuitry, the IC die further having an on-chip test unit to use the I/O buffer circuitry to test at speed (a) an interconnect bus and (b) one of an I/O subsystem and memory subsystem, of the computer system.
- 18. The article of manufacture of claim 17 wherein the core function circuitry is that of a processor core.
- 19. The article of manufacture of claim 17 wherein the core function circuitry is that of a system chipset.
- 20. The article of manufacture of claim 17 wherein the test unit is programmable and provides test results via an on-chip test access port separate from the interconnect bus.
- 21. An article of manufacture comprising:
a machine-readable medium having data that, when accessed by a platform management subsystem of a computer system, cause a plurality of programmable built-in test units, each associated with respective core function circuitry and located in a separate, primary integrated circuit component of the computer system, to be configured for testing, at speed and without requiring an operating system program to boot, a primary component interconnect, a memory subsystem, and an I/O subsystem of the computer system to determine whether electrical specifications of the computer system are met.
- 22. The article of manufacture of claim 21 wherein the medium has further data that, when accessed by the platform management subsystem, cause a test pattern to be loaded into one of the plurality of test units, said test pattern being designed to stress one of the primary component interconnect, memory subsystem, and I/O subsystem.
- 23. The article of manufacture of claim 22 wherein the medium has further data that, when accessed by the platform management subsystem, cause error information to be read from a register of one of the plurality of test units.
- 24. The article of manufacture of claim 22 wherein the medium has further data that, when accessed by the platform management subsystem, cause the platform management subsystem to signal one of the plurality of test units to begin testing.
RELATED APPLICATIONS
[0001] U.S. patent application Ser. No. ______ , Testing Methodology and Apparatus for Interconnects, filed Dec. 16, 2002 (pending).