Claims
- 1. In an integrated RF bipolar transistor formed in a semiconductor body and having a ballast comprising a parallel resistor-capacitor connected to an emitter of the transistor, a method of fabricating the ballast on the semiconductor body comprising the steps of:
- a) forming a resistive layer on a surface of said semiconductor body, said resistive layer contacting the emitter of the transistor at an emitter contact,
- b) depositing a first metal layer on the surface and laterally spaced from the resistive layer, the first metal layer including an extension contacting the resistive layer at a point spaced from the emitter contact, whereby the first metal layer does not overlay the resistive layer except for the extension,
- c) defining a capacitive plate area on said first metal layer on which oxides have been removed,
- d) depositing a dielectric material over said capacitive plate area, and
- e) depositing a second metal layer over said dielectric material and over the first metal layer, the second metal layer functioning as a capacitor plate, said second metal layer having an extension contacting said emitter contact.
- 2. The method as defined by claim 1, wherein step a) forms a polycrystalline silicon layer, and steps b) and e) deposit aluminum metal.
- 3. The method as defined by claim 1, wherein step b) deposits metals from the group consisting of a refractory metal and a refractory metal silicide.
- 4. The method as defined by claim 1, wherein step c) comprises in situ etching of oxides on the capacitive plate area.
- 5. The method as defined by claim 1, wherein step c) comprises depositing a native oxide free material on the capacitive plate area.
- 6. The method as defined by claim 5, wherein the native oxide free material is selected from the group consisting of platinum, platinum silicide and gold.
Parent Case Info
This is a Division of application Ser. No. 08/756,297 filed Nov. 25, 1996 U.S. Pat. No. 5,821,602 the disclosure of which is incorporated by reference.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
Country |
46-23206 |
Jul 1971 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Wolf Stanley, Silicon Processing for the VLSI Era, vol. 1, p. 520, 1990. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
756297 |
Nov 1996 |
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