Patent Application
20190215000
Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, a ring oscillator topology based on a resistor array.
A wireless communication network may include a number of base stations that can support communication for a number of mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station. The base station and/or mobile station may include a frequency synthesizer, which may be implemented with a phase-locked loop (PLL) including a voltage-controlled oscillator (VCO). The VCO may be implemented with a resonant tank circuit or a ring oscillator circuit, for example.
Certain aspects of the present disclosure generally relate to a ring oscillator circuit utilizing selective coupling of resistive elements to tune a frequency of an oscillating signal generated by the ring oscillator circuit.
Certain aspects of the present disclosure provide a ring oscillator circuit. The ring oscillator circuit generally includes one or more delay elements coupled in series, wherein an output of a last one of the delay elements is coupled to an input of an initial one of the delay elements, and a plurality of resistive elements selectively coupled to a tail node of at least a first one of the delay elements, the resistive elements for coarse-tuning a frequency of an oscillating signal generated by the ring oscillator circuit.
Certain aspects of the disclosure provide a method for generating an oscillating signal. The method generally includes operating a ring oscillator circuit comprising one or more delay elements coupled in series, wherein an output of a last one of the delay elements in the ring oscillator circuit is coupled to an input of an initial one of the delay elements in the ring oscillator circuit, and coupling a first set of a plurality of resistive elements to a tail node of at least a first one of the delay elements to set a frequency of the oscillating signal generated by the ring oscillator circuit, the resistive elements for coarse-tuning the frequency.
Certain aspects of the present disclosure provide an apparatus for controlling an oscillating signal. The apparatus generally includes means for generating the oscillating signal using one or more means for delaying a signal coupled in series, wherein an output of a last one of the means for delaying is coupled to an input of an initial one of the means for delaying; means for combining current through at least a first one of the means for delaying; and means for selectively coupling a plurality of resistive elements to the means for combining current to set a frequency of the oscillating signal, the resistive elements for coarse-tuning the frequency.
So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.
Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structures, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
As used herein, the term “connected with” in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B). In the case of electrical components, the term “connected with” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).
Access point 110 may communicate with one or more user terminals 120 at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the access point to the user terminals, and the uplink (i.e., reverse link) is the communication link from the user terminals to the access point. A user terminal may also communicate peer-to-peer with another user terminal. A system controller 130 couples to and provides coordination and control for the access points.
Wireless communications system 100 uses multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. Access point 110 may be equipped with a number Nap of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set Nu of selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and/or receives user-specific data from the access point. In general, each selected user terminal may be equipped with one or multiple antennas (i.e., Nut≥1). The Nu selected user terminals can have the same or different number of antennas.
Wireless communications system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. Wireless communications system 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where the additional cost can be supported).
In certain aspects of the present disclosure, the access point 110 and/or user terminal 120 may include at least one ring oscillator circuit, as described in more detail herein.
On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280. TX data processor 288 processes (e.g., encodes, interleaves, and modulates) the traffic data {dup} for the user terminal based on the coding and modulation schemes associated with the rate selected for the user terminal and provides a data symbol stream {sup} for one of the Nut,m antennas. A transceiver front end (TX/RX) 254 (also known as a radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) a respective symbol stream to generate an uplink signal. The transceiver front end 254 may also route the uplink signal to one of the Nut,m antennas for transmit diversity via an RF switch, for example. The controller 280 may control the routing within the transceiver front end 254. Memory 282 may store data and program codes for the user terminal 120 and may interface with the controller 280.
A number Nup of user terminals 120 may be scheduled for simultaneous transmission on the uplink. Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.
At access point 110, Nap antennas 224a through 224ap receive the uplink signals from all Nup user terminals transmitting on the uplink. For receive diversity, a transceiver front end 222 may select signals received from one of the antennas 224 for processing. The signals received from multiple antennas 224 may be combined for enhanced receive diversity. The access point's transceiver front end 222 also performs processing complementary to that performed by the user terminal's transceiver front end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is an estimate of a data symbol stream {sup} transmitted by a user terminal. An RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for that stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and/or a controller 230 for further processing.
In certain aspects of the present disclosure, the transceiver front end (TX/RX) 222 of access point 110 and/or transceiver front end 254 of user terminal 120 may include a ring oscillator circuit, as described in more detail herein.
On the downlink, at access point 110, a TX data processor 210 receives traffic data from a data source 208 for Ndn user terminals scheduled for downlink transmission, control data from a controller 230 and possibly other data from a scheduler 234. The various types of data may be sent on different transport channels. TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal. TX data processor 210 may provide a downlink data symbol streams for one of more of the Ndn user terminals to be transmitted from one of the Nap antennas. The transceiver front end 222 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver front end 222 may also route the downlink signal to one or more of the Nap antennas 224 for transmit diversity via an RF switch, for example. The controller 230 may control the routing within the transceiver front end 222. Memory 232 may store data and program codes for the access point 110 and may interface with the controller 230.
At each user terminal 120, Nut,m antennas 252 receive the downlink signals from access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 may select signals received from one of the antennas 252 for processing. The signals received from multiple antennas 252 may be combined for enhanced receive diversity. The user terminal's transceiver front end 254 also performs processing complementary to that performed by the access point's transceiver front end 222 and provides a recovered downlink data symbol stream. An RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.
Receiving in-phase (I) or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, the mixer 312, and the DA 314 may be included in a radio frequency integrated circuit (RFIC), while the PA 316 may be external to the RFIC. The BBF 310 filters the baseband signals received from the DAC 308, and the mixer 312 mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process produces the sum and difference frequencies of the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are referred to as the beat frequencies. The beat frequencies are typically in the RF range, such that the signals output by the mixer 312 are typically RF signals, which may be amplified by the DA 314 and/or by the PA 316 before transmission by the antenna 303.
The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, the mixer 324, and the BBF 326 may be included in a radio frequency integrated circuit (RFIC), which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert). The baseband signals output by the mixer 324 may be filtered by the BBF 326 before being converted by an analog-to-digital converter (ADC) 328 to digital I or Q signals for digital signal processing.
While it is desirable for the output of an LO to remain stable in frequency, tuning the LO to different frequencies typically entails using a variable-frequency oscillator, which involves compromises between stability and tunability. Contemporary systems may employ frequency synthesizers with a voltage-controlled oscillator (VCO) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO frequency may be produced by a TX frequency synthesizer 318, which may be buffered or amplified by amplifier 320 before being mixed with the baseband signals in the mixer 312. Similarly, the receive LO frequency may be produced by an RX frequency synthesizer 330, which may be buffered or amplified by amplifier 332 before being mixed with the RF signals in the mixer 324. The VCO in the TX frequency synthesizer 318 and/or the RX frequency synthesizer 330 may be implemented, for example, by a ring oscillator, as described below.
As illustrated in
In some aspects of the present disclosure, as illustrated in
The VCO 402 in the PLL 400 may be implemented, for example, by a ring oscillator circuit, as described below.
Ring oscillators are an economic way to implement frequency synthesis (such as in the TX frequency synthesizer 318 or the RX frequency synthesizer 330 of
Oscillations in a ring oscillator may be controlled during operation thereof. Such control may change the frequency of the oscillation signal generated by the ring oscillator, allowing for circuits using such oscillators to be adaptable to changing environments or different desired frequencies. Ring oscillators, therefore, may be used as voltage-controlled oscillators (VCOs) in circuits for wireless communication devices, for example. In one example control operation, the tuning voltage to the ring oscillator arrangement may be increased. Increases of the tuning voltage, in certain aspects, cause an increase in frequency of the oscillating signal.
A first current mirror circuit includes a biasing current source (labeled “Ibias”), a transistor 502, a low-pass filter, and a plurality of transistors 504, 506, etc. The biasing current source may provide a constant bias current (e.g., 100 μA), which may be adjustable for certain aspects. Transistor 502 is implemented by an n-channel metal-oxide semiconductor (NMOS) transistor. The biasing current source is coupled to the drain of transistor 502, where the drain and the gate of transistor 502 are connected together to form the biasing branch of the first current mirror circuit. The source of transistor 502 is coupled to a reference potential node (e.g., electrical ground as shown) for the oscillator circuit 500. The low-pass filter is implemented by a first-order passive filter comprising series resistor R1 and shunt capacitor C1, as shown in
Fine-tuning of the frequency of the oscillating signal output by the ring oscillator 501 may be provided by a second current mirror circuit. As depicted in
As described above, conventional ring oscillator circuits, such as the oscillator circuit 500, rely on a current tail to adjust for both coarse frequency tuning and fine frequency tuning, which results in a large resistor-capacitor (RC) filter and current mirror area and additional circuits, such as a voltage-to-current converter. Furthermore the flicker noise from the current tail cannot be filtered. Overall, conventional ring oscillator circuits have a large noise and area overhead that can make the ring oscillator circuit less attractive than a resonant tank oscillator circuit, even in non-critical applications.
Certain aspects of the present disclosure provide a ring oscillator circuit that utilizes a resistive element array for coarse frequency tuning and may also employ a variable capacitive element array for fine frequency tuning. Such a topology may eliminate the large layout area for RC filter arrangements, the current mirror(s), and the voltage-to-current converter of conventional ring oscillator circuits. This topology may also achieve better phase noise than conventional topologies while still consuming similar currents at the same frequencies as conventional topologies.
Unlike the transistors in the current tail bank of
For certain aspects (as illustrated in detail in
As illustrated in
With a two-stage ring oscillator circuit, the stages may output quadrature signals. For example, the first delay cell 802 may output a differential in-phase (I) signal (labeled as “I_p” and “I_m”), and the second delay cell 804 may output a differential quadrature (Q) signal (labeled as “Q_p” and “Q_m”), where Q_p is 90° out of phase with I_p and 180° out of phase with Q_m.
Each delay cell may include a head node 821 and a tail node 825. The head node 821 of each delay cell may be used for receiving power from a power supply (e.g., power supply 503). For certain aspects, two or more of the head nodes 821 of the different delay cells may be connected together for receiving power from the same power supply. The tail node 825 of each delay cell may be used for sinking current through the circuit elements in the delay cell, which may control the frequency of the oscillating signal generated by ring oscillator. For certain aspects, two or more of the tail nodes 825 of the different delay cells may be connected together and connected to a current tail bank 806. As described above with respect to
Fine-tuning of the frequency of the oscillating signal for the multi-stage ring oscillator circuit 800 may be accomplished using capacitive elements. In the example of
The operations 900 may begin, at block 902, by operating a ring oscillator circuit comprising one or more delay elements (e.g., delay cells 802, 804) coupled in series. An output of a last one of the delay elements (e.g., the second delay cell 804) in the ring oscillator circuit may be coupled to an input of an initial one of the delay elements (e.g., the first delay cell 802) in the ring oscillator. At block 904, a first set of a plurality of resistive elements (e.g., resistors 602, 604, etc.) may be coupled to a tail node (e.g., tail node 825) of at least a first one of the delay elements to set a frequency of the oscillating signal generated by the ring oscillator circuit. The resistive elements may be used for coarse-tuning the frequency of the oscillating signal.
According to certain aspects, the operations 900 may further entail coupling a second set of the plurality of resistive elements to the tail node to adjust the frequency of the oscillating signal. In this case, at least one of the resistive elements is different between the first and second sets of resistive elements.
According to certain aspects, the operations 900 may further involve activating a first set of a plurality of tunable capacitive elements (e.g., variable capacitive element pairs 810, 812, and/or 814) coupled to an output node (e.g., out_p or out_m) of at least a second one of the delay elements at optional block 906. The tunable capacitive elements may be used for fine-tuning the frequency of the oscillating signal. For certain aspects, the operations 900 may further include activating a second set of the plurality of tunable capacitive elements to adjust the frequency of the oscillating signal. In this case, at least one of the activated tunable capacitive element is different between the first and second sets of the plurality of tunable capacitive elements. For certain aspects, the plurality of tunable capacitive elements comprises a plurality of varactors (e.g., varactors 702 and 704). For certain aspects, the plurality of tunable capacitive elements are AC-coupled to the output node of the at least the second one of the delay elements. For certain aspects, the at least the first one of the delay elements is the same as the at least the second one of the delay elements. For certain aspects, each of the plurality of tunable capacitive elements is coupled between the output node and a different one of a plurality of tuning nodes (e.g., vtune<0>, vtune<1>, and/or vtune<2>) for tuning the capacitive elements. In this case, activating the first set of the plurality of tunable capacitive elements at optional block 906 may involve selectively closing a plurality of switches (e.g., switch S0, S1, and/or S2) according to the first set of tunable capacitive elements. Each of the switches may be coupled between one of the plurality of tuning nodes and a same tuning voltage node (e.g., tuning voltage node 703).
According to certain aspects, coupling the first set of the plurality of resistive elements to the tail node at block 902 entails selectively closing a plurality of switches (e.g., switches 606, 608, etc.) according to the first set. In this case, each of the switches may be connected in series with one of the resistive elements between the tail node and a reference potential node for the ring oscillator circuit.
According to certain aspects, the one or more delay elements include a first delay element (e.g., first delay cell 802) and a second delay element (e.g., second delay cell 804). In this case, an output of the first delay element may be coupled to an input of the second delay element. For certain aspects, the first delay element is the initial one of the delay elements. Also, an output of the second delay element may be the output of the last delay element and may be coupled to the input of the first delay element. For certain aspects, the output of the first delay element provides an in-phase (I) oscillating signal, and the output of the second delay element provides a quadrature (Q) oscillating signal.
Certain aspects of the present disclosure provide a ring oscillator circuit. The ring oscillator circuit generally includes one or more delay elements coupled in series, wherein an output of a last one of the delay elements (in the series) is coupled to an input of an initial one of the delay elements (in the series), and a plurality of resistive elements selectively coupled to a tail node of at least a first one of the delay elements, the resistive elements for coarse-tuning a frequency of an oscillating signal generated by the ring oscillator circuit.
According to certain aspects, the ring oscillator circuit may further include a plurality of tunable capacitive elements coupled to an output node of at least a second one of the delay elements. The tunable capacitive elements may be used for fine-tuning the frequency of the oscillating signal. For certain aspects, the plurality of tunable capacitive elements comprises a plurality of varactors. For certain aspects, the ring oscillator circuit further includes a capacitive element (e.g., capacitor 706 or 708) coupled between the plurality of tunable capacitive elements and the output node of the at least the second one of the delay elements. In this case, the ring oscillator circuit may also include an impedance (e.g., resistor 710 or 712) coupled between the plurality of tunable capacitive elements and a bias node (e.g., bias node 711) associated with the at least the second one of the delay elements. For certain aspects, the at least the first one of the delay elements is the same as the at least the second of the delay elements. For certain aspects, each of the plurality of tunable capacitive elements is coupled between the output node and a different one of a plurality of tuning nodes for tuning the capacitive elements. In this case, each of the plurality of tuning nodes may be selectively coupled to a same tuning voltage node.
According to certain aspects, the ring oscillator circuit may further include a plurality of switches. Each of the switches may be connected in series with one of the resistive elements between the tail node and a reference potential node for the ring oscillator circuit.
According to certain aspects, the one or more delay elements include a first delay element and a second delay element. In this case, an output of the first delay element may be coupled to an input of the second delay element. For certain aspects, the first delay element is the initial one of the delay elements. Also, an output of the second delay element may be the output of the last one of the delay element and may be coupled to the input of the first delay element. For certain aspects, the output of the first delay element provides an in-phase (I) oscillating signal, and the output of the second delay element provides a quadrature (Q) oscillating signal.
Certain aspects of the present disclosure provide a phase-locked loop (PLL) (e.g., the PLL 400). The PLL generally includes a charge pump, a loop filter having an input coupled to an output of the charge pump, and a ring oscillator circuit as described herein, wherein an output of the loop filter is a tuning voltage node (e.g., Vtune).
According to certain aspects, at least one of the delay elements includes a logical inverter. For certain aspects, the logical inverter is a CMOS inverter.
Certain aspects of the present disclosure provide a ring oscillator topology that utilizes a resistor array for coarse frequency tuning and, in some cases, may employ a varactor array for fine frequency tuning. This ring oscillator topology occupies a smaller layout area than conventional current-tail-based ring oscillator topologies and may also consume less current. Additionally, the ring oscillator topology of the present disclosure achieves superior phase noise performance compared to conventional ring oscillators.
The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware component(s) and/or module(s), including, but not limited to one or more circuits. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.
For example, means for generating an oscillating signal may include a ring oscillator, such as the ring oscillator 501 illustrated in
As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), ascertaining, and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, “determining” may include resolving, selecting, choosing, establishing, and the like.
As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).
The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure may be implemented or performed with discrete hardware components designed to perform the functions described herein.
The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.
