Claims
- 1. Ring oscillator having odd numbers of unit inverters,
- said unit inverters comprising:
- first and second inverter portions connected between first and second nodes in parallel, each inverter portion including P channel transistor connected between said first node and an output node thereof outputting a clock signal, and N channel transistor connected between said second node and said output node the output from the output node of said first inverter portion in each stage circulated through the ring, the output from the output node of said second inverter portion in each stage circulated through the ring;
- a first constant current source connected between a voltage source node and said first node; and
- a second constant current source connected between a ground potential node and said second node.
- 2. Ring oscillator having odd numbers of unit inverters,
- said unit inverter comprising:
- first and second inverter portions connected between a first node and a second node connected to a ground potential node in parallel, each inverter portion including P channel transistor connected between said first node and an output node thereof outputting a clock signal, and N channel transistor connected between said second node and said output node the output from the output node of said first inverter portion in each stage circulated through the ring, the output from the output node of said second inverter portion in each stage circulated through the ring; and
- a constant current source connected between a voltage source node and said first node.
- 3. Ring oscillator having odd numbers of unit inverters,
- said unit inverter comprising:
- first and second inverter portions connected between a first node connected to a voltage source node and a second node in parallel, each inverter portion including P channel transistor connected between said first node and an output node thereof outputting a clock signal, and N channel transistor connected between said second node and said output node the output from the output node of said first inverter portion in each stage circulated through the ring, the output from the output node of said second inverter portion in each stage circulated through the ring; and
- a constant current source connected between a ground potential node and said second node.
- 4. Ring oscillator of claim 1, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3 V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4.
- 5. Ring oscillator of claim 2, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3 V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4.
- 6. Ring oscillator of claim 3, wherein
- clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3 V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4.
- 7. Ring oscillator of claim 1, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.2, V.sub.3, V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3.
- 8. Ring oscillator of claim 2, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.2, V.sub.3, V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3.
- 9. Ring oscillator of claim 3, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.2, V.sub.3, V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-137870 |
Jun 1995 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 08/537,120, filed on Sep. 29, 1995, now abandoned.
US Referenced Citations (4)
Continuations (1)
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Number |
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Parent |
537120 |
Sep 1995 |
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