BRIEF DESCRIPTION OF THE DRAWINGS
The above contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
FIG. 1 is a schematic block diagram of a conventional ROM testing system;
FIGS. 2A˜2D are schematic block diagrams illustrating four embodiments of a ROM testing system using a ROM emulator according to the present invention; and
FIG. 3 is a flowchart illustrating a ROM testing method according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.
Referring to any of FIGS. 2A˜2D, a ROM testing system using a multi-interfaced ROM emulator according to an embodiment of the present invention is illustrated. The ROM emulating system comprises a ROM emulator 20, a computer 50 in communication with the ROM emulator 20 via a transmission line 55 and a motherboard 40 where a ROM emulated by the ROM emulator 20 is to be inserted in communication with the ROM emulator 20 via an optional path. For testing the ROM, the motherboard 40 is supposed to read BIOS codes from a ROM mounted therein. Since there is no real ROM inserted into the ROM socket of the motherboard 40, the motherboard 40 reads BIOS codes from a rewritable memory 25 in the ROM emulator 20 through one of a variety of paths 215 (FIG. 2A), 225 (FIG. 2B), 235 (FIG. 2C) and 245 (FIG. 2D) (Step S01), and executes a POST (power on self test) procedure to see how the emulated ROM works with the circuitry of the motherboard 40 (Step S02). If the testing result shows a need to modify the ROM (Step S03), the BIOS codes stored in the rewritable memory 25 in the ROM emulator 20 can be arbitrarily modified by way of the computer 50 (Step S04). The modifying and testing procedures can be repeated as many times as needed until the emulating result is satisfactory (Step S05), as illustrated in the flowchart of FIG. 3.
For implementing the above-described testing method, the ROM emulator 20 is designed with a variety of connectors to communicate with the motherboard 40. For example, the ROM emulator 20 includes an ISA connector 21, an LPC connector 22, a general-purpose bus connector such as PCI connector 23 and a test port connector 24. If the ROM socket of the motherboard 40 is of an ISA specification, as shown in FIG. 2A, the ROM emulator 20 can be made communicable with the motherboard 40 by coupling the ISA connector 21 to the ISA ROM socket 42 via an ISA transmission line 215. On the other hand, if the ROM socket of the motherboard 40 is of an LPC specification, as shown in FIG. 2B, the ROM emulator 20 can be made communicable with the motherboard 40 by coupling the LCP connector 22 to the LPC ROM socket 43 via an LPC transmission line 225.
If the motherboard 40 supports a PCI (Peripheral Component Interconnect) specification, the ROM emulator 20 can alternatively be inserted into a PCI slot 44 of the motherboard 40 via the PCI connector 23, as shown in FIG. 2C, no matter whether the ROM socket of the motherboard 40 is of an ISA or LPC specification. In a further embodiment as shown in FIG. 2D, the ROM emulator 20 can alternatively be inserted into a test port 46 of the motherboard 40 via the test port connector 24 no matter whether the ROM socket of the motherboard 40 is of an ISA or LPC specification. For example, the test port 46 can be an LPC male port while the test port connector 24 is an LPC female port. In these two embodiments, direct connection 235 or 245 can be made between the ROM emulator 20 and the motherboard 40, exempting from the use of any transmission line.
It is understood by those skilled in the art that the above sockets 42, 43, PCI slot 44 and test port 46 are optionally disposed in the motherboard 40. Of course, they can be co-existent in the motherboard 40, and one of the connecting means is selected and coupled to the ROM emulator 20 for testing.
In addition to the connectors 21, 22, 23 and 24, the ROM emulator 20 further includes the rewritable memory 25 to which the computer 50 may access so as to modify the BIOS codes, and a controller 26 coupled to the connectors 21, 22, 23 and 24 and rewritable memory 25 for controlling the data transmission between the connectors 21, 22, 23 and 24 and rewritable memory 25 so as to allow the motherboard 40 to successfully read and execute BIOS codes stored in the rewritable memory 25 via one of the connectors 21, 22, 23 and 24. The rewritable memory 25, for example, can be an ASRAM (Asynchronous Static Random Access Memory) or a flash memory. The controller 26 is an ASIC (Application Specific Integrated Circuit) controller or a CPLD (Complex Programmable Logic Device) controller.
Moreover, the ROM emulator 20 further includes a transmission port 27 and a transmission port controller 28 to communicate with the computer 50 through the transmission line 55. The transmission port 27 and transmission line 55, for example, can be a USB (Universal Serial Bus) port and a USB transmission line to enable high-speed BIOS-code loading from the computer 50 to the rewritable memory 25. The transmission port controller 28, for example, can be a USB+8051 controller coupled between the transmission port 27 and the controller 26. The BIOS codes are transmitted from the transmission port 27 to the controller 26, and then written into the rewritable memory 25 under the control of the controller 26. When the controller 26 loads the BIOS codes to the rewritable memory 25, the BIOS codes will be optionally converted into a proper format, e.g. ISA or LPC, by the controller 26 to be stored in the rewritable memory 25, depending on the data storage format of the rewritable memory 25.
For example, referring to FIG. 2A, the ROM socket 42 is of an ISA specification and the rewritable memory 25 transmits data in an ISA format. Since the signal definitions of these two devices are both parallel and their access clock signals are compatible, the controller 26 does not have to convert the format of the BIOS codes but directly transfers the BIOS codes from the rewritable memory 25 to the motherboard 40 via the connector 21, the transmission line 215 and ROM socket 42. Meanwhile, the controller 26 will adjust the signal level received from the motherboard 40, e.g. from +5V to +3.3V) to comply with the level requirement of the rewritable memory 25, and vice versa, adjust the signal level read from the rewritable memory 25, e.g. from +3.3V to +5V, to comply with the level requirement of the motherboard 40. Furthermore, the controller 26 buffers the control signal transmitted from the motherboard 40 and the BIOS codes transmitted from the computer 50 so as to avoid collision.
In anther example as illustrated in FIG. 2B, the ROM socket 43 is of an LPC specification, which is a serial format, while the rewritable memory 25 transmits data in a parallel ISA format. Under this circumstance, the controller 26 needs to conduct a conversion between the LPC and ISA interfaces so as to achieve coincidence in signal definition and access clock. First of all, the control signal asserted by the motherboard 40 is converted from a serial format into a parallel format and the access clock signal is adjusted from 33 MHz into 8 MHz by the controller 26 in order to comply with the requirement of the rewritable memory 25 for reading the BIOS codes. Then the controller 26 converts the BIOS codes read from the rewritable memory 25 from the parallel format into serial format. Meanwhile, the controller 26 also adjusts the access clock signal from 8 MHz into 33 MHz to allow the BIOS codes to be successfully transmitted via the connector 22, transmission line 225 and ROM socket 43 to be executed by the motherboard 40.
In a further example as illustrated in FIG. 2C, the ROM emulator 20 is directly inserted into the PCI slot 44 with the PCI-pin connector 23 to save space and simplify the connecting operation. In this case, the controller 26 needs to make proper conversion between the PCI and ISA specification. Although PCI and ISA specifications are both in a parallel format, some factors including the access clock are still required adjustment. Therefore, the controller 26 first conducts PCI/ISA conversion of the control signal asserted by the motherboard 40 with the adjustment of the access clock from 33 MHz to 8 MHz or from 66 MHz to 8 MHz. Subsequently, the controller 26 reads BIOS codes from the rewritable memory 25 while transforming the transmission format from ISA to PCI and adjusting the access clock from 8 MHz to 33 MHz or 66 MHz, thereby allowing the BIOS codes to be successfully transmitted from the rewritable memory 25 to the motherboard 40 via the connector 23 and PCI slot 43.
Likewise, in a yet another example as illustrated in FIG. 2D, the ROM emulator 20 is directly coupled into the additional test port 46, which is of a LPC specification, so the controller 26 needs to convert the control signal asserted by the motherboard 40 into the format identifiable by the rewritable memory 25, and then converts the BIOS codes read from the rewritable memory 25 into the format identifiable by the motherboard 40. Accordingly, the BIOS codes can be successfully transmitted from the rewritable memory 25 to the motherboard 40 to be executed via the connector 24 and test port 46.
In the above embodiments, the motherboard 40, after realizing identifiable BIOS codes from the rewritable memory 25, executes a POST (power on self test) procedure to see whether the emulated ROM well works with the circuitry of the motherboard 40. During the test procedure, post/debug codes are optionally generated and transmitted to I/O ports of the motherboard 40, e.g. the I/O ports at addresses 80 h and 84 h. Meanwhile, the ROM emulator 20 picks up and decodes the post/debug codes, and informs the designer of the decoded data, for example, by the displays 30 and/or 35. The displays 30 and 35 can be seven-segment displays. By way of the displays 30 and 35, the designer is able to realize the post/debug codes and decoded data directly without the use of an additional debug card, which is generally inserted into a PCI slot, to show the test result. In general, the transmission of debug codes, like the control signal and BIOS codes, may need conversion depending on the transmission specifications of the motherboard 40 and ROM emulator 20.
From the above description, it is understood a ROM emulator of the present invention is multi-interfaced and provides a variety of connection paths to communicate with a motherboard for testing a ROM emulated by the present ROM emulator to be inserted into the motherboard. Therefore, the applications of the present ROM emulator are diversified. Furthermore, since the ROM adapter used in the prior art is omitted, the space utility of the ROM testing system is enhanced. Moreover, in addition to the connection to a ROM socket via a transmission line, the ROM emulator can also be directly inserted into the motherboard through an interface such as a PCI slot or test port so as to save space, cost and laboring. Aside from, the provision of one or more displays in the present ROM emulator for showing test results will facilitate the designer's work.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not to be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Patent Application
20080021695
