Patent Application
20150293767
1. Field of the Disclosure
The present disclosure relates to rotating register files and, specifically, to rotating register files with bit expansion support.
2. Description of the Related Art
In processor architectures designed to employ parallelism, very long instruction word (VLIW) architectures are known for having relatively simple hardware complexity and enabling various functionality through compiler software, such as software pipelining, where the program includes the decisions that determine how instructions are executed in parallel. With software pipelining, scheduling decisions may be made in a VLIW architecture at compile time.
In some VLIW processor designs, rotating register files are used to facilitate writing loop unrolling code by providing hardware support using a register pointer for physical index conversion. As the register pointer is incremented, the physical register mapping is incremented by a fixed amount for loop increments. However, such conventional rotating register files may not be well suited when data expansion occurs within a loop, such as multiplication of two 16-bit data values resulting in a 32-bit data value, which may involve different update increment values for the register pointer. One known solution has been to use two separate register files with respective separate register pointers, for example, one for 16-bit data and another for 32-bit data. However, such a scheme using different register files may not be economical in terms of hardware resource efficiency. Accordingly, there is a need in the art for a flexible rotating register file that is not limited to a fixed register pointer increment.
In one aspect, a disclosed method for accessing a rotating register file with bit expansion support in a processor includes dividing a register file into a plurality of regions, assigning a plurality of register pointers respectively to each of the regions, and assigning a plurality of increment values respectively to each of the register pointers. During execution of processor instructions, the method may include incrementing the register pointers respectively according to the increment values.
In another aspect, a disclosed method of using a rotating register file with bit expansion support in a processor includes setting a plurality of increment values respectively for each of a plurality of register pointers. The plurality of increment values may include at least two different values. The method may include setting a plurality of regions of a register file respectively for each of the register pointers. Responsive to incrementing an instruction pointer for a next instruction, the method may include determining which of the register pointers corresponds to a virtual register number for the next instruction, calculating a physical register number in the register file, and rotating the register pointers through each of the regions respectively according to the increment values.
Additional disclosed aspects for implementing a rotating register file with bit expansion support include non-transitory computer-readable memory media storing instructions executable in a processor, and a memory accessible to the processor storing executable instructions, and a processor implementing a rotating register file with bit expansion support.
In the following description, details are set forth by way of example to facilitate discussion of the disclosed subject matter. It should be apparent to a person of ordinary skill in the field, however, that the disclosed embodiments are exemplary and not exhaustive of all possible embodiments.
Throughout this disclosure, a hyphenated form of a reference numeral refers to a specific instance of an element and the un-hyphenated form of the reference numeral refers to the element generically or collectively. Thus, for example, widget 12-1 refers to an instance of a widget class, which may be referred to collectively as widgets 12 and any one of which may be referred to generically as a widget 12.
In a conventional rotating register file, a physical index to a register file in a processor may be calculated using a virtual register index and a register pointer. The register pointer may be incremented by 1 at each process execution, causing the physical indices to rotate through the register file. Such functionality may be useful for software optimizations, such as loop unrolling and/or software pipelining.
Thus, conventional rotating register files may be limited to a fixed register pointer increment, which may be disadvantageous for certain kinds of looped operations, such as when data expansion occurs within a loop. As will be described herein, the inventors of the present disclosure have discovered a rotating register file with bit expansion support. The rotating register file with bit expansion support described herein may enable dividing a rotating register file into arbitrary regions and may assign different register pointer to each divided region. Each of the register pointers may have different update increments, such as 0, 1, or 2, depending on a desired data bit width and a corresponding program attribute. In this manner, registers may be flexibly assigned using desired regions according to individual program requirements. Using the rotating register file with bit expansion support described herein, a single rotating register file may be used to handle 2, 4, 8, etc. sets of registers or may remain undivided with a single set using all the registers.
Turning now to the drawings,
As shown in
In the example embodiment of register file 100 shown in
In Program 2, load.iu is a load data with immediate address update command, mult_hp is a multiply high precision command, add_hp_c is an add high precision and cut command, and store.iu is a store data with immediate address update command. In certain instances, Program 2 may be implemented in an 8-way VLIW architecture using register file 100. An example of an 8-way VLIW pipeline is shown in Table 1, which may include 4 load/store words, 2 multiply words, 1 arithmetic logic word, and 1 register pointer update word.
Program 3 shows how an implementation of the loop body of Program 2, comprising 7 operations, is assigned to an 8-way VLIW where 1 of the 8 ways is reserved for the register pointer update.
As evident in Program 3, using register file 100, the loop body of Program 2 may be executed in parallel, since register file 100 has been divided to support both 16-bit and 32-bit data values. In
As shown in
Register Entry=Offset+{VirtualRegisterNumber−Offset+AssignedRegisterNumber} % NumberofAssignedRegisters Equation 1: Register Entry Calculation
For example, using Equation 1 for register index w7 at rp0=9, the following values may result in a register entry=0:
In another example, using Equation 1 for register index w18 at rp1=18, the following values may result in a register entry=20:
Referring now to
Method 200 may begin by dividing (operation 202) a register file in a processor into a plurality of regions. A plurality of register pointers may be respectively assigned (operation 204) to each of the regions. A plurality of increment values may be respectively assigned (operation 206) to each of the register pointers. The increment values may include at least two different increment values. The increment values may include a zero increment value. Each register pointer may be incremented (operation 208) according to the respective increment value, while register entries are rotated through each of the regions independently according to the increment values. A physical register number corresponding to a register pointer may be output (operation 210) and the register file may be accessed (operation 210) according to the physical register number.
Turning now to
Method 300 may begin by setting (operation 302) a plurality of increment values respectively for each of a plurality of register pointers. Then, a plurality of regions of a register file may be set (operation 304) respectively for each of the register pointers. An instruction pointer may be increment (operation 306) for a next instruction. Method 300 may then determine (operation 308) which of the register pointers corresponds to a virtual register number for the next instruction. A physical register number may be calculated (operation 310) from an offset, a virtual register number, a number of assigned registers, and an assigned register pointer value. The physical register number corresponding to a register pointer may be output (operation 312) and the register file may be accessed (operation 312) according to the physical register number.
Referring now to
As shown in
As disclosed herein, a method and system for implementing rotating register files with bit expansion support may enable a plurality of register pointers, each with a respective increment value, to be implemented in a register file of a processor. The register pointers may correspond to different regions of the register file. Each region of the register file may have a different size.
The above disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments which fall within the true spirit and scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present disclosure is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
