Routing for Microprocessor Busses

Abstract

This invention provides means and methods for improving the routing and multiplexing logic of microprocessor busses and other similar high fan logic functions in FPGA and ASIC circuits. Routing of high fan-in signals is simplified by distributing the multiplexing function. The multiplexing function is separated into an AND function in the logic block and a programmable OR function in the routing block. Programming bits control which signals are ORed together in the routing elements. The AND output of a peripheral is controlled by either a distributed control circuit or by control signal(s) from a centralized control circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1: is a simplified schematic block diagram of a typical FPGA architecture.

FIG. 2: Programmable Interconnect and Horizontal wires

FIG. 3: A Simple Programmable Interconnect Element

FIG. 4: A Multiplexer Based Programmable Interconnect

FIG. 5: Timing Improvement from Repeaters

FIG. 6: Altera Stratix Logic Function

FIG. 7: The Xilinx CLB

FIG. 8: Xilinx XC3000 Routing Resources

FIG. 9: Programmable Interconnect Points and Local Interconnections

FIG. 10: Construction of Programmable Interconnect Points (PIPS) and Switch Matrices

FIG. 11: I/O Routing

FIG. 12: Basic Xilinx V2Pro Routing

FIG. 13: Xilinx Direct Connections

FIG. 14: Xilinx V2Pro double lines

FIG. 15: Xilinx V2Pro “hex lines” and “long lines”

FIG. 16 Processor Connections

FIG. 17: A Simple Microprocessor Bus

FIG. 18: Multiplexer for High Fan In signals

FIG. 19: Tree of 4 Input Multiplexers

FIG. 20: Basic Embodiment of the Invention

FIG. 21: Conventional Multiplexer Tree in an FPGA

FIG. 22: Routing of Signals

FIG. 23: The output AND function in a Xilinx like Logic Element

FIG. 24: Implementation of Routing Element

FIG. 25: RAM block with AND outputs

FIG. 26: Transfer Gated replaced by OR function with Repeaters

FIG. 27: An alternate embodiment incorporating the AND function in the output routing function

FIG. 28: Preferred Embodiment of a Microprocessor Peripheral in an FPGA

FIG. 29: Data Output Routing of Distributed RAM

FIG. 30: Logic Element Configuration for Efficient CAM Implementation

FIG. 31: Hierarchical Construction of a Large ASIC

FIG. 32: Routing Within a Hierarchical Block

DETAILED DESCRIPTION OF THE INVENTION AND THE PREFERRED EMBODIMENT

The preferred embodiment of the invention comprises the addition of an AND element and buffer to the output of the logic element of an FPGA, a routing element that utilized unidirectional signals and incorporates an OR function, RAM blocks with AND elements and buffers for the output pins, and microprocessor(s) with AND elements and buffers for the output pins.

Logic Element

FIG. 23 illustrates the addition of an output AND function to a Xilinx like logic element in accordance with the present invention.

The AND function in the logic element acts as an enable or disable for the output signal when connected to the OR implemented in the routing elements. In the preferred embodiment the enable input to the AND function is connected to the input routing element.

Routing Element

FIG. 24 shows a routing element that incorporates OR functions that can be used in a hierarchical routing system. This routing element consists of eight programmable OR functions (2401). Signals can enter the routing element from any of four directions. For convenience, these directions are referred to as “North, South, East, and West. Signals entering the routing element from the North, East, of South on either of two inputs e.g. a double or hex line can be ORed together and propagated to the west on either of two outputs. Which signals contribute to the OR function is controlled by programming bits.

Application to a RAM Block

Since the RAM elements in stare of the art FPGAs are frequently connected to high fan in signals such as microprocessor data busses the RAM blocks should also be modified to contain AND based outputs. FIG. 25 illustrates a RAM similar to the Altera Tri matrix RAM and Xilinx Block RAM. The AND function and repeater added to the Data Out circuit enables the use of the improved routing element. The Xilinx Distributed RAM, as described in Xilinx Virtex-4 RAM is implemented in the logic function and can take advantage of the output AND function shown in FIG. 23.

Application to a Processor

The high fan in busses of a microprocessor including the data output bus and address bus for processors that support external bus masters should also incorporate an AND function in the output buffers to take advantage of this invention.

Output Routing

FIG. 26 illustrates the use of an OR function to replace the transfer gates conventionally used to connect the logic functions to the adjacent routing.

The bi-directional transfer gate and single wire has been replaced by two unidirectional wires and logic gates. In this example timing will be improved over the transfer gate based interconnect due to repeater insertion as shown in FIG. 5. The circuit of FIG. 26 can also be used to interconnect logic elements that are not adjacent i.e. logic elements 2, 3, or 6 rows of columns away.

Application to a Soft IP Core

FIG. 28 illustrates a microprocessor peripheral designed to take advantage of the invention. The AND functions used in the Data in connection will be implemented in the AND function in the Logic Elements.

Application to Distributed RAM

FIG. 29 illustrates the data output routing of a 64 word by 4 bit distributed RAM using logic elements with an AND function in the output (2901) and OR function in the routing element (2902). This use of the invention will result in a more efficient distributed RAM since no additional logic elements are required to interconnect the outputs. Address inputs and “chip select” signals will still be routed conventionally (2903).

No Logic Functions and only one routing channel per output bit are used in this example. This greatly simplifies the interconnection of multiple distributed RAMs into larger arrays. This interconnection is useful in structures such as FIFOs and register files in addition to connection to a microprocessor.

Simplified CAM Implementation

Content Addressable Memories (CAM) consumes extensive logic and routing resources when implemented in current FPGAs. This invention allows for an efficient CAM in an FPGA. The distributed OR function can be used to implement an equivalent to the high fan in “wired AND” function conventionally used to implement match lines in a CAM. To take full advantage of this capability the logic element should allow configuration the interconnections in the logic element as shown in FIG. 30.

Application to ASICs and Structured ASICs

While the description of this invention is focused on the implementation of high fan in functions in FPGAs it will be apparent to one skilled in the art that the same techniques can be applied to ASICs, Structured ASICs and full custom designs. Modern ASIC and full custom designs are hierarchically structured. FIG. 31 illustrates a typical ASIC (in this case a specialized microprocessor incorporating communications interfaces).

Some of these components incorporate a large number of registers and memories connected to wide high fan in busses.

In a typical ASIC design the major components will be assigned so areas on the chip. This process is referred to as floor planning. Floor planning may also assign locations for the connection of specific interface signals. Once floor planning is done low level gates and standard cells that make up the individual components are placed and routed. After the major components have been placed and routed the connections between the major components are routed. Because the connections between major components are long large ASIC designs require “repeater insertion” for high performance (FIG. 5).

This invention can be applied to internal routing in the major components and the interconnection between the components. Internal to the major components OR functions can be placed at locations where two or more signals that comprise a high fan in network join as shown in FIG. 32.

Software for Routing an FPGA or ASIC

FPGAs and ASICs are typically routed using Automatic Place Route software. APR software typically involves complex routing algorithms that attempt to determine a set of routes for all signals in a design that meets the timing goals specified as “timing constraints” by the user. For high fan-in signals these FPGA routing algorithms can be modified to take advantage of the OR functions in the routing elements as follows:

• • All of the signals that are part of a high fan in network (the input and output signals of the OR functions) are first routed as though they were a single network containing no logic functions.
  • The OR function of a routing element where two or more signals from CLBs or other OR functions join to create another output signal in enabled.

For ASICs the OR functions within major blocks can be placed as part of the placement program using conventional methods such as:

• • Force directed placement
  • Simulated annealing

The OR functions can also be placed to produce wire equal length or equal delay (wire delay plus gate delay) trees.

Alternatively the OR functions can be placed and routed as part of the routing process similar to repeater insertion. In this case the method described for FPGAs will be used with the additional step of inserting the OR functions where multiple nets join.

The inter-component placement of OR functions and routing can be performed using any of the methods described for ASIC components though performing it as part of routing and repeater insertion is preferred since the OR functions will act as repeaters.

It will be understood that the forgoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the AND and OR functions described herein and in the claims may be implemented by use of NAND/NAND, NOR/NOR or other logical equivalents to implement the disclosed invention and related means and methods. Furthermore, the term “amplifier” includes the use of a “repeater”; and an “ASIC” includes the use of a “structured ASIC”.

Claims

1. A method for routing signals comprising: use of a distributed AND function in the logic elements of a FPGA; anduse of a distributed OR function in the routing components of a FPGA.

2. The method of claim 1 using the AND function at the output stage of the logic function.

3. The method of claim 1 using the AND function in the output routing element.

4. The method of claim 1 used as a method of implementing a wide multiplexer and a wide multiplexer's routing in a FPGA.

5. The method of claim 1 connecting one or more inputs of the AND function to the combinatorial logic function in the logic element of an FPGA.

6. The method of claim 1 connecting one or more inputs of the AND function to the input routing element.

7. The method of claim 1 incorporating the AND function in a dedicated RAM or microprocessor.

8. The method of claim 7 incorporating the AND function used in a hard core in a FPGA.

9. The method of claim 1 using the distributed AND and OR functions on a subset of the interconnect.

10. The method of claim 1 connecting the storage elements in FPGA logic elements and the output AND function to implement a binary or ternary CAM cell.

11. The method of claim 10 using the OR function in the routing element as an “as wired AND”.

12. The method of claim 1 wherein the OR function includes the use of an amplifier.

13. A method of implementing a fan-in function and a fan-in function's associated routing in an ASIC comprising: use of a distributed AND function used in the logic elements and marco cells; anduse of a distributed OR function used in the routing components.

14. A method of assigning a routing attribute to signals that connect to a high fan function comprising: a) routing the signals as if they were a single signal; andb) using the signal's attribute to indicate to the place and route tools where to: 1) enable the OR functions in an FPGA;2) insert an OR function in an ASIC; and3) replace a repeater with an OR function.

15. The method of claim 14 wherein the initial signal routing is performed using a conventional routing algorithm and the OR function of the routing element of an FPGA or ASIC is enabled in the routing elements where two or more signals are joined together.

16. A device for implementing a multiplexer and the multiplexer's routing in an FPGA, comprising: a distributed AND function used in the logic elements of the of the FPGA; anda distributed OR function used in the routing components of the FPGA.

17. The device of claim 16 wherein the AND function is used at the output stage of the logic function.

18. The device of claim 16 wherein the AND function is used in the output routing element.

19. The device of claim 16 wherein one or more inputs of the AND function are connected to the combinatorial logic function in a logic element of a FPGA.