Claims
- 1. A method for decreasing capacitive cross coupling in sequentially addressed data lines, comprising:
providing said data lines in subset groupings; and ordering each of said subset groupings such that at least one of said data lines in each of said subset groupings is not physically adjacent to any of said data lines in same subset groupings which will switch generally simultaneously therewith.
- 2. The method of claim 1, and further including:
providing a ground trace between any of said data lines an any adjacent of said data lines which will switch generally simultaneously therewith.
- 3. The method of claim 1, and further including:
providing a ground trace between each of said subset groupings.
- 4. The method of claim 1, wherein:
the quantity of data lines in each of said subset groupings is four.
- 5. The method of claim 1, wherein:
said sequentially addressed data lines are row enable lines in a video pixel array.
- 6. In a decoder for sequentially enabling output data lines for a pixel array, an improvement comprising:
traces physically arranged such that the occurrence of sequentially switching traces is reduced.
- 7. The decoder of claim 6, wherein:
the traces are physically arranged such that the occurrence of sequentially switching traces is reduced.
- 8. The decoder of claim 6, wherein:
the traces are physically arranged in an order B, D, A, C where the sequential order of switching is A, B, C, D.
- 9. The decoder of claim 6, wherein:
the traces are physically arranged in an order A, C, D, B where the sequential order of switching is A, B, C, D.
- 10. The decoder of claim 6, wherein:
the traces are physically arranged in an order C, A, D, B where the sequential order of switching is A, B, C, D.
- 11. The decoder of claim 6, wherein:
the traces are physically arranged in an order B, D, A, C where the sequential order of switching is A, B, C, D.
- 12. The improvement of claim 6, wherein:
said traces are the physical traces of an integrated circuit chip.
- 13. The improvement of claim 6, wherein:
said traces are the output of a predecoder.
- 14. The improvement of claim 6, wherein:
the predecoder accepts two inputs to cause one of four of said traces to go high, depending upon the combination of states of the two inputs.
- 15. The improvement of claim 6, wherein:
the quantity of traces is sufficient to address all rows of the pixel array.
- 16. The improvement of claim 6, wherein:
the total quantity of traces is embodied in sets of four.
- 17. The improvement of claim 16, and further including:
a plurality of ground traces physically placed such that one of said ground traces is between each of the sets of four output data lines.
- 18. The improvement of claim 17, wherein:
the output data lines and the ground traces are each traces on an integrated circuit.
- 19. A predecoder having four outputs which are enabled sequentially in the order A, B, C, D, comprising:
a data line for each of the four outputs such that the data lines may be designated as A line, B line, C line and D line, respectively; wherein one of said A line and said D line are disposed between said B line and said D line.
- 20. The predecoder of claim 19, wherein:
the data lines provide input to a row decoder for enabling rows of a pixel array.
RELATED APPLICATIONS
[0001] This application is a divisional of copending U.S. patent application Ser. No. 09/075,447, filed on May 8, 1998, by the same inventor, which is incorporated herein by reference in its entirety.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09075447 |
May 1998 |
US |
Child |
09894119 |
Jun 2001 |
US |