Row and/or column decoder optimization method and apparatus

Abstract

A row decoder (10) for a video display system (12) wherein row output lines (28) of a row predecoder (20) are physically arranged such that adjacent iterations of the output lines (28) will generally not be switching simultaneously where addressing of the output lines (28) is sequential according to numbering and application. A ground trace (32) is provided between iterations of the output lines (28) which will be switching simultaneously. The output lines (28) provide input to a decoding circuit (34) within the row decoder (10). A plurality iterations of predecoder subcircuits (21) each having a compliment of the output lines (28) is to provided such that all of the rows of a pixel array (14) can be addressed.

Description

TECHNICAL FIELD

The present invention relates to the field of electronic circuitry, and more particularly to address decoders such as are used for decoding row or column information in a video display device. The predominant current usage of the inventive optimized row decoder is in the decoding of row information in video display devices wherein the ability to rapidly change states is important.

BACKGROUND ART

Row and column decoders are well known in the art for activating rows and columns in array devices. Many array devices are memory arrays, and the technology of row decoders has, in great part, been developed for use with such memory devices. Another type of array device is the array display device. This category includes liquid crystal display (“LCD”) devices. In general, a row decoder is used to activate a particular row of the display such that data present on a plurality of column lines will affect the intended row. To date, the row and column decoders used with such video display devices are not substantially different in concept from comparable devices which are used in conjunction with memory array devices.

Another device known in the field is the predecoder. One skilled in the art will recognize that a predecoder will allow a required amount of binary data to be transmitted on fewer data lines than might be required if the data were not to be “predecoded”. For example, four different row addresses can be referenced according to the four different logical state combinations of two data lines.

It is known in the art that capacitive interaction between adjoining data lines will substantially detract from the ability of such lines to change state rapidly. Where one line of two adjacent lines is changing state, this is somewhat of a problem. However, where the two adjacent lines are simultaneously attempting to change states in opposite direction (one is going high, while the other is going low), this problem is severely compounded, especially when the adjacent lines are long.

It would be a significant improvement if a method or apparatus were found to decrease the detrimental effect caused by the simultaneous state changes of adjacent data lines within a row or column decoder. This is particularly important given the present quest for increased speed and/or lower power consumption. (In this case, as in many such instances, there is a trade off between speed and power consumption. That is, a decrease in the capacitive interaction between adjacent lines could be used to cause greater operational speed for a given applied power. Alternatively, less power could be used to achieve the same speed, or some combination of improved speed and power consumption could be accomplished.) However, to the inventor's knowledge, no such improvement in the design of row and column decoders has been presented prior to the present invention.

DISCLOSURE OF INVENTION

Accordingly, it is an object of the present invention to provide a row and/or column decoder which will change states faster than comparable prior art decoders.

It is still another object of the present invention to provide a row and/or column decoder which can achieve a desired speed using less power than prior art devices.

It is yet another object of the present invention to provide a method and apparatus for reducing the effect of sideways capacitive coupling in adjacent data lines in particular applications.

It is still another object of the present invention to provide a method and apparatus for improving the performance of row and/or column decoders which does not effectively increase the cost of producing the decoders.

It is yet another object of the present invention to provide a method and apparatus for improving the performance of row and/or column decoders which does not take up a great deal of real estate on an integrated circuit.

Briefly, an embodiment of the present invention is an improved row decoder for a video display device which has row addressing lines configured such that no two adjacent lines will be switching states simultaneously. The invention takes advantage of the fact that the rows of the video display device, unlike rows or columns of memory array devices, will generally be switching sequentially. That is, the rows are addressed in order, for example beginning at the top of a screen and progressing in order to the bottom of the screen. This makes possible the inventive physical layout.

An advantage of the present invention is that video display devices can be caused to operate more quickly.

A further advantage of the present invention is that row and/or column decoders can be operated using less power.

Yet another advantage of the present invention is that it can be readily implemented into existing row and/or column decoder designs without extensive modification.

These and other objects and advantages of the present invention will become clear to those skilled in the art in view of the description of the described mode of carrying out the invention and the industrial applicability of the embodiment as described herein and as illustrated in the several figures of the drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block schematic diagram of a portion of a video display system including the present inventive improved row decoder;

FIG. 2 is a schematic diagram of a predecoder subcircuit as used in the video display system of FIG. 1 ;

FIG. 3 is a block schematic diagram of a portion of a row decoder and predecoder assembly according to the present invention; and

FIG. 4 is a table showing some possible variations in the arrangement of data lines according to the present inventive method and apparatus.

DETAILED DESCRIPTION OF THE INVENTION

The invention is embodied in an improved row decoder 10 , which is depicted in box schematic form in the view of FIG. 1 , for use in a video display system 12 such as is used for displaying a computer video output or other video image such as a television picture. One skilled in the art will recognize that the video display system 12 , such as might employ the present inventive improved row decoder 10 , will have many components which are conventional and well known in the art. In part, the video display system 12 will have, in addition to the improved row decoder 10 , a pixel array 14 , a data router 16 , a row sequencer 38 and, in the embodiment depicted in FIG. 1 , a row predecoder 18 .

In the video display system 12 of FIG. 1 , the data router 16 routes data to columns of the pixel array 14 . The data router 16 is described in detail in a copending patent application Ser. No. 08/970,443, which is incorporated by reference herein. It should be noted, however, that the present invention is not dependent upon any particular method or apparatus for supplying data to the columns of the pixel array 14 . The row decoder 10 enables rows of the pixel array 14 such that data provided through the data router 16 will affect the particular row of the pixel array 14 which is intended.

FIG. 2 is a schematic diagram of a predecoder subcircuit 21 which will form a portion of the predecoder 18 of FIG. 1 , as will be discussed in greater detail hereinafter. In the view of FIG. 2 , it can be seen that two input data lines 22 provide data to four nand gates 24 . In this embodiment two inverters 26 invert the state of the data lines 22 . One skilled in the art will recognize that another common method, not shown, would be to separately provide inverted inputs such that inversion within the predecoder 20 would not be required. Either configuration could be employed in conjunction with the present inventive row decoder 10 .

Although it is not necessary to the practice of the invention, in the embodiment shown, each of four output lines 28 has three output inverters 30 for increasing the gain of the signal on the output lines 28 and, since an odd number of the output inverters 30 is employed on each output line 28 , for inverting the output of the nand gates 24 . One skilled in the art will recognize that one of the four output lines 28 will be high, depending upon which of the four logical combinations of binary states in which the two input data lines 22 exist. Specifically, in the embodiment depicted, the output lines (at the points designated by “RX” in the view of FIG. 2 ) will be as follows: When both inputs A< 0 > and A< 1 > are low, then RX< 0 > will be high; when A< 0 > is high and A< 1 > is low, then RX< 1 > will be high; when A< 0 > is low and A< 1 > is high, then RX< 2 > will be high; and when both inputs A< 0 > and A< 1 > are high, then RX< 3 > will be high.

It should be noted that, in the actual embodiment of the video display system 12 of FIG. 1 , the pixel array 14 is anticipated to be 1024 columns by 768 rows in size. Whatever the quantity of rows in a particular application, the quantity of iterations of the circuit shown in the view of FIG. 2 should be provided which is sufficient to address all of the rows of the intended pixel array 14 . In the example of 768 rows, five iterations of the predecoder subcircuit ( 21 ) will be employed to provide the ten data bits necessary to address the 768 rows.

FIG. 3 is a block schematic diagram showing an example of a portion of the row predecoder 20 and the improved row decoder 10 of FIG. 1 . One skilled in the art of integrated circuit design will recognize that the electrical schematic of the predecoder subcircuit 21 depicted in FIG. 2 is an electrical schematic only, and does not dictate how the components thereof are to be laid out in a circuit chip. According to the described example of the present invention, the several iterations of the predecoder subcircuit 21 utilized will be laid out such that the output lines 28 are positioned, as depicted in the view of FIG. 3 , in the following sequence: RX< 1 >, RX< 3 >, RX< 0 >, RX< 2 >. (That is, were the output lines 28 to be designated as A, B, C, D, respectively according to the order in which they are switched high, then the physical layout would be sequentially: B, D, A, C. Between each RX< 3 > and the adjacent RX< 0 > is a ground trace 32 .

It should be noted that results similar (but not equal to) some of the advantages of the present invention might be achieved by simply placing iterations of the ground traces 32 between each and all of the output lines 28 and also between each set thereof. However, this would not be practical for reasons including that it would require additional real estate on the chip, and additional expense.

A decoding circuit 34 of the row decoder 10 is a conventional decoder circuit such as is found in the prior art and is not affected by the present invention except that the decoding circuit 34 may operate faster as described herein. The decoding circuit 34 contains the logic to take as input the plurality (in the case of the present example, five) sets of four output lines 28 from the predecoder subcircuits 21 and enable a particular row of the pixel array 14 as intended. It should be noted that, in the view of FIG. 1 , a single decoder output 36 is shown to represent the plurality (one per row) of outputs from the decoder circuitry 34 ( FIG. 3 ) to the pixel array 14 . Similarly, in the view of FIG. 1 , a single pre-decoder input 38 is used to represent the input data lines 22 of FIG. 3 . Other data routes which are not specifically discussed in relation to FIG. 1 are also represented by a single line even though one skilled in the art will recognize that these are generally busses which will have therein a plurality of data paths.

In light of the above description, it will be recognized that where only one of the four output lines 28 of each predecoder subcircuit 21 is to be high at any given time, then it will be likely according to prior art arrangements that adjacent output lines 28 will be switching simultaneously. That is, were output lines designated as A, B, C and D to be laid out and switched in that order, then after B is high, then C would be going high while B would simultaneously be going back low. However, according to the present inventive apparatus and method, the inventor has discovered that no two adjacent output lines 28 will be changing state simultaneously (with the exceptions such as those discussed hereinafter in relation to FIG. 4 . which will have a ground trace 32 therebetween.) This depends upon the condition, which is typical in the described application, that switching of the output lines 28 will be sequential (that is, sequential according to the numbering and usage, but not sequential according to the present inventive layout). In prior art memory array applications, or in any application wherein switching of the output lines 28 is random rather than sequential, the present invention would not provide the intended benefit.

FIG. 4 is a table depicting the logical sequences of arrangements of the four output lines 28 for sequential sets of the predecoder subcircuits 21 where each of the predecoder subciruits has the output lines 28 arranged in like order. This is by no means an exclusive list of the scope of the invention since variations such as having different sets of output lines 28 arranged in different orders are quite likely useful. Also, the present invention is in no way restricted to applications wherein the quantities are as described in relation to the examples herein. As just one example, in some applications it is likely that quantities of output lines 28 per row predecoder other than four are possible.

In the table of FIG. 4 , the rows 40 (enumerated as “a” through “x”, inclusive) represent the various possible physical arrangement of the output lines 28 which will switch in the order “0, 1, 2, and then 3”. A right hand column 42 of the table of FIG. 4 indicates the quantity of ground traces 32 per set (equivalent to all of the outputs of one of the predecoder subcircuits 21 ) that will be required due to the fact that adjacent output lines 28 will be switched consecutively (and will, therefore, be switching simultaneously). In the table of FIG. 4 , the ground traces are represented by an “x” within the table. Note that the upper case “X” indicates a ground trace 32 between the sets 21 . This is merely an effort to make the table of FIG. 4 more readily understandable. In practice, there is not significant difference between ground traces 32 between the output lines 28 within a set 21 and ground traces 32 between the sets.

In the table of FIG. 4 it can be seen that the sequences designated by rows 40 (d), (i), (q) and (u) are optimal in the sense that these require the fewest quantity of ground traces. The example of row 40 (i) is that which has previously been discussed herein in relation to FIG. 3 .

It should be noted that, between adjacent sets 21 , it is possible to have some arrangements wherein adjacent output lines would be switching in the same direction simultaneously. This would produce a reinforcing effect which could actually cause the output lines 28 to switch faster than might otherwise be the case. The inventors have found that this is also generally an undesirable condition, since it might interfere with the overall timing and stability of the circuit and, therefore, ground traces 32 should generally also be placed between sets 21 where this condition would otherwise occur.

One skilled in the art will recognize that the present invention is applicable to any decoder or subdecoder for decoding sequential values, and is not limited to the decoding of display addresses.

As previously mentioned herein, the present invention can be applied equally to column decoders as well as row decoders, were the column decoders to be addressed in a sequential or other ordered pattem. Indeed, in some applications the terms “row” and “column” have less meaning than in the typical video display array application, and such terms may be used interchangeably.

While the invention as described herein is embodied as a portion of an integrated circuit, the invention could also be applied to other physical embodiments. Indeed, if there were to be an application wherein the sort of switching lines falling within the scope of the invention were to be laid out on a printed circuit board, then the advantages described herein could be attained.

The inventor has discovered that the present inventive method and apparatus will result in less than one third the cross coupling between adjacent output lines 28 as compared to prior art instances wherein adjacent output lines 28 are switching in opposite directions simultaneously.

Various modifications may be made to the invention without altering its value or scope. As just one example, the actual predecoder circuitry depicted by way of the example of FIG. 2 is not necessary to the practice of the present invention, and any conceivable arrangement for providing the groups of output lines 28 which can be physically arranged according to the present inventive method might be employed for the purpose.

Yet another example of a potential variation of the invention would be in an application wherein sequential switching of lines other than those intended for addressing the rows or columns of an array is intended. Although the inventor does not have in mind any such specific application, it is anticipated that the invention could be effectively applied thereto were such an application to arise.

All of the above are only some of the examples of available embodiments of the present invention. Those skilled in the art will readily observe that numerous other modifications and alterations may be made without departing form the spirit and scope of the invention. Accordingly, the above disclosure is not intended as limiting and the appended claims are to be interpreted as encompassing the entire scope of the invention.

Claims

1. A decoder device, comprising:a plurality of input lines for receiving data; a plurality of output data lines; and decoder logic operative to enable one of said output data lines depending on said data received on said input lines; and wherein responsive to a sequential stream of data being asserted on said input lines said output data lines are enabled in consecutive order, and wherein said output data lines are physically arranged in non-consecutive order.

2. The decoder device of claim 1, wherein:the quantity of output data lines is four, such that said output data lines can be designated as A, B, C and D, respectively where the designations A, B, C and D designate the order in which said output data lines are enabled responsive to said sequential stream of data; and said four output data lines are physically arranged in the order B, D, A, C.

3. The decoder device of claim 2, and further including:a ground trace interposed between data line D and data line A.

4. The decoder device of claim 1, wherein:the quantity of output data lines is four, such that said output data lines can be designated as A, B, C and D, respectively where the designations A, B, C and D designate the order in which said output data lines are enabled responsive to said sequential stream of data; and said four output data lines are physically arranged in the order A, C, D, B.

5. The decoder device of claim 4, and further including:a ground trace interposed between data line C and data line D.

6. The decoder device of claim 1, wherein:the quantity of output data lines is four, such that said output data lines can be designated as A, B, C and D, respectively where the designations A, B, C and D designate the order in which said output data lines are enabled responsive to said sequential stream of data; and said four output data lines are physically arranged in the order C, A, D, B.

7. The decoder device of claim 6, and further including:a ground trace interposed between data line A and data line D.

8. The decoder device of claim 1, wherein:the quantity of output data lines is four, such that said output data lines can be designated as A, B, C and D, respectively where the designations A, B, C and D designate the order in which said output data lines are enabled responsive to said sequential stream of data; and said four output data lines are physically arranged in the order D, B, A, C.

9. The decoder device of claim 6, and further including:a ground trace interposed between data line B and data line A.

10. The decoder device of claim 1, and further including:a plurality of iterations of said plurality of input lines; a plurality of iterations of said plurality of output data lines; and a plurality of iterations of said decoder logic.

11. The decoder device of claim 10, and further including:a ground trace between each iteration of said plurality of output data lines.

12. The decoder device of claim 1, wherein:said decoder logic is a predecoder circuit and; said plurality of output data lines provide said enable signals to additional decoder logic.

13. The decoder device of claim 12, wherein:the quantity of said input lines is two; and each of said input lines has two potential states.

14. The decoder device of claim 1, wherein:the quantity of said output data lines is four; each of said four output data lines has two potential states those being high and low; and only one of said four output data lines is going high at any given time.

15. The decoder device of claim 1, wherein:said plurality of output data lines are enabling lines for enabling rows of a video pixel array.