Patent Grant
12301793
In spite of the advances in video compression, digital video still accounts for the largest bandwidth use on the internet and other digital communication networks. As the number of connected user devices capable of receiving and displaying video increases, it is expected that the bandwidth demand for digital video usage will continue to grow.
The present document describes various embodiments for buffer management and block vector coding for intra block copy mode for decoding or encoding video or images.
In one example aspect, a method of visual media processing is disclosed. The method includes determining, for a conversion between a current video block of a current picture of a visual media data and a bitstream representation of the current video block, a block vector (BVx, BVy), wherein validity of the block vector (BVx, BVy) is independent of (1) a location (P, Q) of a sample block and/or (2) whether a sample at the location (P, Q) is reconstructed, and/or (3) a location of the current video block, wherein, the block vector (BVx, BVy) represents a pixel displacement between the current video block and the sample block; and performing, using the block vector, the conversion in an intra block copy mode which is based on a reconstructed block located in same video region with the current video block comprising reference samples used for deriving a prediction block of the current video block, wherein, during the conversion, a prediction sample with a location (A, B) from reference samples in a buffer is determined at least according to a size of the buffer and/or the block vector (BVx, BVy).
In another example aspect, another method of visual media processing is disclosed. The method includes determining, for a conversion between a current video block of a current picture of a visual media data and a bitstream representation of the visual media data, whether a block vector (BVx, BVy) corresponding to the current video block is valid according to a rule, wherein the block vector (BVx, BVy) represents a pixel displacement between the current video block and a sample block; and performing, using the block vector, the conversion based on a reference region from the current picture comprising reference samples used for deriving a prediction block of the current video block, wherein the rule specifies that the block vector (BVx, BVy) is valid in case that (1) one or more samples from the sample block are outside the current picture and/or (2) one or more samples from the sample block are outside at least one coding tree unit (CTU) associated with the current video block, and/or (3) one or more samples from the sample block fail to be reconstructed.
In yet another example aspect, another method of visual media processing is disclosed. The method includes performing a conversion between a current video block of a current picture of a visual media data and a bitstream representation of the visual media data, wherein, the conversion is based on a reference region from the current picture comprising reference samples used for deriving a prediction block of the current video block, and wherein a virtual buffer of a defined size is used for tracking availability of the reference samples for deriving the prediction block.
In yet another example aspect, another method of visual media processing is disclosed. The method includes maintaining, for a conversion between a current video block of a current picture of a visual media data and a bitstream representation of the visual media data, a buffer comprising reference samples from the current picture for a derivation of a prediction block of the current video block, wherein one or more reference samples in the buffer that are marked unavailable for the derivation have values outside of a pixel value range.
In another example aspect, another method of video processing is disclosed. The method includes performing a conversion between a current video block of a current picture of a visual media data and a bitstream representation of the visual media data using a buffer comprising reference samples from the current picture for derivation of a prediction block of the current video block, wherein the conversion is based according to rule which specifies that, for the bitstream representation to conform the rule, a reference sample in the buffer is to satisfy a bitstream conformance constraint.
In yet another example aspect, a video encoder or decoder apparatus comprising a processor configured to implement an above described method is disclosed.
In another example aspect, a computer readable program medium is disclosed. The medium stores code that embodies processor executable instructions for implementing one of the disclosed methods.
These, and other, aspects are described in greater detail in the present document.
Section headings are used in the present document for ease of understanding and do not limit scope of the disclosed embodiments in each section only to that section. The present document describes various embodiments for buffer management and block vector coding for intra block copy mode for decoding or encoding video or images.
This patent document is related to video coding technologies. Specifically, it is related to intra block copy in video coding. It may be applied to the standard under development, e.g., Versatile Video Coding (VVC). It may be also applicable to future video coding standards or video codec.
Video coding standards have evolved primarily through the development of the well-known International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) and International Organization for Standardization (ISO)/International Electrotechnical Commission (IEC) standards. The ITU-T produced H.261 and H.263, IS O/IEC produced Moving Picture Experts Group (MPEG)-1 and MPEG-4 Visual, and the two organizations jointly produced the H.262/MPEG-2 Video and H.264/MPEG-4 Advanced Video Coding (AVC) and H.265/HEVC standards. Since H.262, the video coding standards are based on the hybrid video coding structure wherein temporal prediction plus transform coding are utilized. To explore the future video coding technologies beyond HEVC, Joint Video Exploration Team (JVET) was founded by Video Coding Experts Group (VCEG) and MPEG jointly in 2015. Since then, many new methods have been adopted by JVET and put into the reference software named Joint Exploration Model (JEM). In April 2018, the Joint Video Expert Team (JVET) between VCEG (Q6/16) and ISO/IEC JTC1 SC29/WG11 (MPEG) was created to work on the VVC standard targeting a 50% bitrate reduction compared to HEVC.
Each inter-predicted picture unit (PU) has motion parameters for one or two reference picture lists. Motion parameters include a motion vector (MV) and a reference picture index. Usage of one of the two reference picture lists may also be signalled using inter_pred_idc. Motion vectors may be explicitly coded as deltas relative to predictors.
When a coding unit (CU) is coded with skip mode, one PU is associated with the CU, and there are no significant residual coefficients, no coded motion vector delta or reference picture index. A merge mode is specified whereby the motion parameters for the current PU are obtained from neighboring PUs, including spatial and temporal candidates. The merge mode can be applied to any inter-predicted PU, not only for skip mode. The alternative to merge mode is the explicit transmission of motion parameters, where motion vector (to be more precise, motion vector differences (MVD) compared to a motion vector predictor), corresponding reference picture index for each reference picture list and reference picture list usage are signalled explicitly per each PU. Such a mode is named advanced motion vector prediction (AMVP) in this disclosure.
When signalling indicates that one of the two reference picture lists is to be used, the PU is produced from one block of samples. This is referred to as ‘uni-prediction’. Uni-prediction is available both for P-slices and B-slices.
When signalling indicates that both of the reference picture lists are to be used, the PU is produced from two blocks of samples. This is referred to as ‘bi-prediction’. Bi-prediction is available for B-slices only.
The following text provides the details on the inter prediction modes specified in HEVC. The description will start with the merge mode.
Current picture referencing (CPR), or once named as intra block copy (IBC), has been adopted in HEVC screen content coding extensions (HEVC-SCC) and the current VVC test model (VTM). IBC extends the concept of motion compensation from inter-frame coding to intra-frame coding. As demonstrated in
Following a BV to find its reference block, the prediction can be generated by copying the reference block. The residual can be generated by subtracting the reference pixels from the original signals. Then transform and quantization can be applied as in other coding modes.
However, when a reference block is outside of the picture, or overlaps with the current block, or outside of the reconstructed area, or outside of the valid area restricted by some constraints, part or all pixel values are not defined. Basically, there are two solutions to handle such a problem. One is to disallow such a situation, e.g., in bitstream conformance The other is to apply padding for those undefined pixel values. The following sub-sections describe the solutions in detail.
In the screen content coding extensions of HEVC, when a block uses current picture as reference, it should guarantee that the whole reference block is within the available reconstructed area, as indicated in the following spec text:
The variables offsetX and offsetY are derived as follows:
offsetX=(ChromaArrayType==0)?0:(mvCLX[0]&0×7?2:0) (8-104)
offsetY=(ChromaArrayType==0)?0:(mvCLX[1]&0×7?2:0) (8-105)
It is a requirement of bitstream conformance that when the reference picture is the current picture, the luma motion vector mvLX shall obey the following contraints:
Thus, the case that the reference block overlaps with the current block or the reference block is outside of the picture will not happen. There is no need to pad the reference or prediction block.
In a VVC test model, the whole reference block should be with the current coding tree unit (CTU) and does not overlap with the current block. Thus, there is no need to pad the reference or prediction block.
When dual tree is enabled, the partition structure may be different from luma to chroma CTUs. Therefore, for the 4:2:0 color format, one chroma block (e.g., CU) may correspond to one collocated luma region which have been split to multiple luma CUs.
The chroma block could only be coded with the CPR mode when the following conditions shall be true:
If any of the two conditions is false, the chroma block shall not be coded with CPR mode.
It is noted that the definition of ‘valid BV’ has the following constraints:
In some examples, the reference area for CPR/IBC is restricted to the current CTU, which is up to 128×128. The reference area is dynamically changed to reuse memory to store reference samples for CPR/IBC so that a CPR/IBC block can have more reference candidate while the reference buffer for CPR/IBC can be kept or reduced from one CTU.
Suppose that the current luma CU's position relative to the upper-left corner of the picture is (x, y) and block vector is (BVx, BVy). In the current design, if the BV is valid can be told by that the luma position ((x+BVx)>>6<<6+(1<<7), (y+BVy)>>6<<6) has not been reconstructed and ((x+BVx)>>6<<6+(1<<7), (y+BVy)>>6<<6) is not equal to (x>>6<<6, y>>6<<6).
The basic idea of in-loop reshaping (ILR) is to convert the original (in the first domain) signal (prediction/reconstruction signal) to a second domain (reshaped domain).
The in-loop luma reshaper is implemented as a pair of look-up tables (LUTs), but only one of the two LUTs needs to be signalled as the other one can be computed from the signalled LUT. Each LUT is a one-dimensional, 10-bit, 1024-entry mapping table (1D-LUT). One LUT is a forward LUT, FwdLUT, that maps input luma code values Yi to altered values Yr:Yr=FwdLUT[Yi]. The other LUT is an inverse LUT, InvLUT, that maps altered code values Yr to Ŷi:Ŷi=InvLUT[Yr]. (Ŷi represents the reconstruction values of Yi.).
Conceptually, piecewise linear (PWL) is implemented in the following way:
Let x1, x2 be two input pivot points, and y1, y2 be their corresponding output pivot points for one piece. The output value y for any input value x between x1 and x2 can be interpolated by the following equation:
y=((y2−y1)/(x2−x1))*(x−x1)+y1
In fixed point implementation, the equation can be rewritten as:
y=((m*x+2FP_PREC−1)>>FP_PREC)+c
where m is scalar, c is an offset, and FP_PREC is a constant value to specify the precision.
In some examples, the PWL model is used to precompute the 1024-entry FwdLUT and InvLUT mapping tables; but the PWL model also allows implementations to calculate identical mapping values on-the-fly without pre-computing the LUTs.
A method of the in-loop luma reshaping provides a lower complexity pipeline that also eliminates decoding latency for block-wise intra prediction in inter slice reconstruction. Intra prediction is performed in reshaped domain for both inter and intra slices.
Intra prediction is always performed in reshaped domain regardless of slice type. With such arrangement, intra prediction can start immediately after previous transform unit (TU) reconstruction is done. Such arrangement can also provide a unified process for intra mode instead of being slice dependent.
16-piece PWL models are tested for luma and chroma residue scaling instead of the 32-piece PWL models.
Inter slice reconstruction with in-loop luma reshaper (shaded blocks indicate signal in reshaped domain: luma residue; intra luma predicted; and intra luma reconstructed).
Luma-dependent chroma residue scaling is a multiplicative process implemented with fixed-point integer operation. Chroma residue scaling compensates for luma signal interaction with the chroma signal. Chroma residue scaling is applied at the TU level. More specifically, the following applies:
The average is used to identify an index in a PWL model. The index identifies a scaling factor cScaleInv. The chroma residual is multiplied by that number.
It is noted that the chroma scaling factor is calculated from forward-mapped predicted luma values rather than reconstructed luma values.
The parameters are (currently) sent in the tile group header (similar to adaptive loop filter (ALF)). These reportedly take 40-100 bits.
In some examples, the added syntax is highlighted in italics.
In 7.3.2.1 Sequence parameter set RBSP syntax
In 7.3.3.1 General tile group header syntax
Add a new syntax table tile group reshaper model:
[ i ]
In General sequence parameter set RBSP semantics, add the following semantics:
In tile group header syntax, add the following semantics
Add tile_group_reshaper_model( ) syntax
When reshape_model_bin_delta_sign_CW_flag[i] is not present, it is inferred to be equal to 0.
The variable RspDeltaCW[i]=(1 2*reshape_model_bin_delta_sign_CW [i])*reshape_model_bin_delta_abs_CW[i];
The variable RspCW[i] is derived as following steps:
The variable OrgCW is set equal to (1<<BitDepthY)/(MaxBinIdx+1).
The value of RspCW[i] shall be in the range of 32 to 2*OrgCW−1 if the value of BitDepthY is equal to 10.
The variables InputPivot[i] with i in the range of 0 to MaxBinIdx+1, inclusive are derived as follows:
InputPivot[i]=i*OrgCW
The variable ReshapePivot[i] with i in the range of 0 to MaxBinIdx+1, inclusive, the variable ScaleCoef[i] and InvScaleCoeff[i]with i in the range of 0 to MaxBinIdx, inclusive, are derived as follows:
The variable ChromaScaleCoef[i] with i in the range of 0 to MaxBinIdx, inclusive, are derived as follows:
At the encoder side, each picture (or tile group) is firstly converted to the reshaped domain And all the coding process is performed in the reshaped domain. For intra prediction, the neighboring block are in the reshaped domain; for inter prediction, the reference blocks (generated from the original domain from decoded picture buffer) are firstly converted to the reshaped domain Then the residuals are generated and coded to the bitstream.
After the whole picture (or tile group) finishes encoding/decoding, samples in the reshaped domain are converted to the original domain, then deblocking filter and other filters are applied.
Forward reshaping to the prediction signal is disabled for the following cases:
Current block is intra-coded.
Current block is coded as CPR (current picture referencing, aka intra block copy, IBC).
Current block is coded as combined inter-intra mode (CIIP) and the forward reshaping is disabled for the intra prediction block.
In the current design of CPR/IBC, some problems exist.
In some embodiments, a regular buffer can be used for CPR/IBC block to get reference.
A function isRec(x,y) is defined to indicate if pixel (x,y) has been reconstructed and be referenced by IBC mode. When (x,y) is out of picture, of different slice/tile/brick, isRec(x,y) returns false; when (x,y) has not been reconstructed, isRec(x,y) returns false. In another example, when sample (x,y) has been reconstructed but some other conditions are satisfied, it may also be marked as unavailable, such as out of the reference area/in a different VPDU, and isRec(x,y) returns false.
A function isRec(c, x,y) is defined to indicate if sample (x,y) for component c is available. For example, if the sample (x, y) has not yet been reconstructed, it is marked as unavailable. In another example, when sample (x,y) has been reconstructed but some other conditions are satisfied, it may also be marked as unavailable, such as it is out of picture/in a different slice/tile/brick/in a different VPDU, out of allowed reference area. isRec(c, x,y) returns false when sample (x, y) is unavailable, otherwise, it returns true.
In the following discussion, the reference samples can be reconstructed samples. It is noted that ‘pixel buffer’ may response to ‘buffer of one color component’ or ‘buffer of multiple color components’.
Reference Buffer for CPR/IBC
Denote the width and height of an IBC buffer as Wbuf and Hbuf. For a W×H block (may be a luma block, chroma block, CU, TU, 4×4, 2×2, or other subblocks) starting from (X, Y) relative to the upper-left corner of a picture, the following may apply to tell if a block vector (BVx, BVy) is valid or not. Let Wpic and Hpic be the width and height of a picture and; Wctu and Hctu be the width and height of a CTU. Function floor(x) returns the largest integer no larger than x. Function isRec(x, y) returns whether sample (x, y) has been reconstructed.
The following, the width and height of a VPDU is denoted as WVPDU (e.g., 64) and HVPDU (e.g., 64), respectively in luma samples. Alternatively, WVPDU and/or HVPDU may denote the width and/or height of another video unit (e.g., CTU).
An implementation of the buffer for IBC is described below.
The buffer size is 128×128. CTU size is also 128×128. For coding of the 1st CTU in a CTU row, the buffer is initialized with 128 (for 8-bit video signal). For coding of the k-th CTU in a CTU row, the buffer is initialized with the reconstruction before loop-filtering of the (k−1)-th CTU.
When coding a block starting from (x,y) related to the current CTU, a block vector (BVx, BVy)=(x−x0, y−y0) is sent to the decoder to indicate the reference block is from (x0,y0) in the IBC buffer. Suppose the width and height of the block are w and h respectively. When finishing coding of the block, a w×h area starting from (x,y) in the IBC buffer will be updated with the block's reconstruction before loop-filtering.
Suppose that CTU size is W×W, an implementation of IBC buffer with size mW×W and bit-depth being B, at the decoder is as below.
At the beginning of decoding a CTU row, initialize the buffer with value (1<<(B−1)) and set the starting point to update (xb, yb) to be (0,0).
When a CU starting from (x, y) related to a CTU upper-left corner and with size w×h is decoded, the area starting from (xb+x, yb+y) and w×h size will be updated with the reconstructed pixel values of the CU, after bit-depth aligned to B-bit.
After a CTU is decoded, the starting point to update (xb, yb) will be set as ((xb+W) mod mW, 0).
When decoding an IBC CU with block vector (BVx, BVy), for any pixel (x, y) related to a CTU upper-left corner, its prediction is extracted from the buffer at position ((x+BVx) mod mW, (y+BVy) mode W) after bit-depth alignment to the bit-depth of prediction signals.
In one example, B is set to 7, or 8 while the output/input bit-depth of the block may be equal to 10.
For a luma CU or joint luma/chroma CU starting from (x,y) related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(((x+BVx)>>6<<6)+128−(((y+BVy)>>6)&1)*64+(x%64), ((y+BVy)>>6<<6)+(y%64)) is true.
For a chroma CU starting from (x,y) related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(((x+BVx)>>5<<5)+64−(((y+BVy)>>5)&1)*32+(x%32), ((y+BVy)>>5<<5)+(y%32)) is true.
For a chroma block or sub-block starting from (x,y) in 4:2:0 format related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(c, (x+BVx+64, y+BVy) is true, where c is a chroma component.
For a chroma block or sub-block starting from (x,y) in 4:4:4 format related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(c, (x+BVx+128, y+BVy) is true, where c is a chroma component.
For a luma CU or joint luma/chroma CU starting from (x,y) related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(((x+BVx)>>6<<6)+128−(((y+BVy)>>6)&1)*64+(x%64), ((y+BVy)>>6<<6)+(y%64)) is true.
For a chroma block or sub-block starting from (x,y) in 4:2:0 format related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(c, ((x+BVx)>>5<<5)+64−(((y+BVy)>>5)&1)*32+(x%32), ((y+BVy)>>5<<5)+(y%32)) is true, where c is a chroma component.
This embodiment highlights an implementation of keeping two most coded VPDUs in the 1st VPDU row and one most coded VPDU in the 2nd VPDU row of a CTU/CTB row, excluding the current VPDU.
When VPDU coding order is top to bottom and left to right, the reference area is illustrated as in
When VPDU coding order is left to right and top to bottom and the current VPDU is not to the right side of the picture boundary, the reference area is illustrated as in
When VPDU coding order is left to right and top to bottom and the current VPDU is to the right side of the picture boundary, the reference area may be illustrated as
Given a luma block (x, y) with size w×h, a block vector (BVx, BVy) is valid or not can be told by checking the following condition:
isRec(((x+BVx+128)>>6<<6)−(refy&0x40)+(x%64), ((y+BVy)>>6<<6)+(refy>>6==y>>6)?(y%64):0), where refy=(y&0x40)?(y+BVy):(y+BVy+w−1).
If the above function returns true, the block vector (BVx, BVy) is invalid, otherwise the block vector might be valid.
If CTU size is 192×128, a virtual buffer with size 192×128 is maintained to track the reference samples for IBC.
A sample (x, y) relative to the upper-left corner of the picture is associated with the position (x%192, y%128) relative to the upper-left corner of the buffer. The following steps show how to mark availability of the samples associate with the virtual buffer for IBC reference.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
If CTU size is 128×128 or CTU size is greater than VPDU size (e.g., 64×64 in current design) or CTU size is greater than VPDU size (e.g., 64×64 in current design), a virtual buffer with size 192×128 is maintained to track the reference samples for IBC. In the following, when a <0, (a%b) is defined as floor(a/b)*b, where floor (c) returns the largest integer no larger than c.
A sample (x, y) relative to the upper-left corner of the picture is associated with the position (x%192, y%128) relative to the upper-left corner of the buffer. The following steps show how to mark availability of the samples associate with the virtual buffer for IBC reference.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
If CTU size is S×S, S is not equal to 128, let Wbuf be equal to 128*128/S. A virtual buffer with size WbufxS is maintained to track the reference samples for IBC. The VPDU size is equal to the CTU size in such a case.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
If CTU size is 128×128 or CTU size is greater than VPDU size (e.g., 64×64 in current design) or CTU size is greater than VPDU size (e.g., 64×64 in current design), a virtual buffer with size 256×128 is maintained to track the reference samples for IBC. In the following, when a<0, (a%b) is defined as floor(a/b)*b, where floor(c) returns the largest integer no larger than c.
A sample (x, y) relative to the upper-left corner of the picture is associated with the position (x%256, y%128) relative to the upper-left corner of the buffer. The following steps show how to mark availability of the samples associate with the virtual buffer for IBC reference.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
When CTU size is not 128×128 or less than 64×64 or less than 64×64, the same process applies as in the previous embodiment, i.e., embodiment #14.
An IBC reference availability marking process is described as follows. The changes are indicated in bolded, underlined, italicized text in this document.
This process is invoked when decoding a coding unit coded in IBC prediction mode.
Inputs to this process are:
For each coding subblock at subblock index (xSbIdx, ySbIdx) with xSbIdx=0 . . . numSbX−1, and ySbIdx=0 . . . numSbY−1, the following applies:
Inputs to this process are:
Output of this process are
This is identical to the previous embodiment except for the following changes:
.
The changes in some examples are indicated in bolded, underlined, text in this document.
When all the following conditions are true, the history-based motion vector predictor (HMVP) list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138),
.
,
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
:
Inputs to this process are:
Output of this process a reconstructed picture sample array recSamples
.
Depending on the value of the color component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
The changes in some examples are indicated in bolded, underlined, italicized text in this document.
When all the following conditions are true, the history-based motion vector predictor list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138),
.
.
,
,
.
,
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
.
:
This process is invoked when decoding a coding unit coded in IBC prediction mode.
Inputs to this process are:
Outputs of this process are:
Inputs to this process are:
Output of this process a reconstructed picture sample array recSamples
.
Depending on the value of the color component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
The changes in some examples are indicated in bolded, underlined, text in this document.
When all the following conditions are true, the history-based motion vector predictor list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138),
.
.
,
.
,
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
.
:
This process is invoked when decoding a coding unit coded in IBC prediction mode.
Inputs to this process are:
Inputs to this process are:
Output of this process are a reconstructed picture sample array recSamples and IBC buffer arrays ibcBufL, ibcBufCb, ibcBufCr.
Depending on the value of the color component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
The changes in some examples are indicated in bolded, underlined, italicized text in this document.
When all the following conditions are true, the history-based motion vector predictor list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138),
.
,
.
,
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
u[ 0 ] =(mvL[ 0 ] +mvd[ 0 ] +2 18) % 2 18 (8-885) mvL[ 0 ] =(u[ 0 ] >=2 17) ? (u[ 0] — 2 18) : u[ 0 ] (8-886) u[ 1 ] =(mvL[ 1 ] +mvd[ 1 ] +2 18) % 2 18 (8-887) mvL[ 1 ] =(u[ 1 ] >=2 17) ? (u[ 1]— 2 18) :u[ 1 ] (8-888) NOTE 1— The resulting values of mvL[ 0 ] and mvL[ 1 ] as specified above will always be in the range of —2 17 to 2 17 — 1, inclusive.
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
.
:
This process is invoked when decoding a coding unit coded in IBC prediction mode.
Inputs to this process are:
Inputs to this process are:
Output of this process are a reconstructed picture sample array recSamples and IBC buffer arrays ibcBufL, ibcBufCb, ibcBufCr.
Depending on the value of the color component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
The following clauses describe some example preferred features implemented by embodiments of method 600 and other methods. Additional examples are provided in Section 4 of the present document.
Additional embodiments and examples of clauses 37 to 41 are described in Item 7 in Section 4.
Additional embodiments and examples of clauses 42 to 43 are described in Items 28 to 31 and 34 in Section 4.
Additional embodiments and examples of clause 4 are described in Item 35 in Section 4.
Additional embodiments and examples of clause 4 are described in Item 36 in Section 4.
Items 23-30 in the previous section provide additional examples and variations of the above clauses 58-62.
The bitstream representation corresponding to a current video block need not be a contiguous set of bits and may be distributed across headers, parameter sets, and network abstraction layer (NAL) packets.
In Section A, we present another example embodiment in which the current version of the VVC standard may be modified for implementing some of the embodiments described in the present document.
This section analyzes several issues in the current IBC reference buffer design and presents a different design to address the issues. An independent IBC reference buffer is proposed instead of mixing with decoding memory. Compared with the current anchor, the proposed scheme shows −0.99%/−0.71%/−0.79% AI/RA/LD-B luma BD-rate for class F and −2.57%/−1.81%/−1.36% for 4:2:0 TGM, with 6.7% memory reduction; or −1.31%/−1.01%/−0.81% for class F and −3.23%/−2.33%/−1.71% for 4:2:0 TGM with 6.7% memory increase.
Intra block copy, i.e., IBC (or current picture referencing, i.e., CPR previously) coding mode, is adopted. It is realized that IBC reference samples should be stored in on-chip memory and thus a limited reference area of one CTU is defined. To restrict the extra on-chip memory for the buffer, the current design reuses the 64×64 memory for decoding the current VPDU so that only 3 additional 64×64 blocks' memory is needed to support IBC. When CTU size is 128×128, currently the reference area is shown in
In the current draft (VVC draft 4), the area is defined as
Thus, the total reference size is a CTU.
The current design assumes to reuse the 64×64 memory for decoding the current VPDU and the IBC reference is aligned to VPDU memory reuse accordingly. Such a design bundles VPDU decoding memory with the IBC buffer. There might be several issues:
To address issues listed in the above sub-section, we propose to have a dedicated IBC buffer, which is not mixed with decoding memory.
For 128×128 CTU, the buffer is defined as 128×128 with 8-bit samples, when a CU (x, y) with size w×h has been decoded, its reconstruction before loop-filtering is converted to 8-bit and written to the w×h block area starting from position (x% 128, y% 128). Here the modulo operator % always returns a positive number, i.e., for x<0, x% L−(−x% L), e.g., −3% 128=125.
Assume that a pixel (x,y) is coded in IBC mode with BV=(BVx, BVy), it is prediction sample in the IBC reference buffer locates at ((x+BVx)% 128, (y+BVy)% 128) and the pixel value will be converted to 10-bit before prediction.
When the buffer is considered as (W, H), after decoding a CTU or CU starting from (x, y), the reconstructed pixels before loop-filtering will be stored in the buffer starting from (x% W, y% H). Thus, after decoding a CTU, the corresponding IBC reference buffer will be updated accordingly. Such setting might happen when CTU size is not 128×128. For example, for 64×64 CTU, with the current buffer size, it can be considered as a 256×64 buffer. For 64×64 CTU,
In such a design, because the IBC buffer is different from the VPDU decoding memory, all the IBC reference buffer can be used as reference.
When the bit-depth of the IBC buffer is 8-bit, compared with the current design that needs 3 additional 10-bit 64×64 buffer, the on-chip memory increase is (8*4)/(10*3)−100%=6.7%.
If we further reduce the bit-depth. The memory requirement can be further reduced. For example, for 7-bit buffer, the on-chip memory saving is 100%−(7*4)/(10*3)=6.7%.
With the design, the only bitstream conformance constraint is that the reference block shall be within the reconstructed area in the current CTU row of the current Tile.
When initialization to 512 is allowed at the beginning of each CTU row, all bitstream conformance constraints can be removed.
In some embodiments, the disclosed methods can be implemented using VTM-4.0 software.
For a 10-bit buffer implementation and common test conditions (CTC), the decoder is fully compatible to the current VTM4.0 encoder, which means that the proposed decoder can exactly decode the VTM-4.0 CTC bitstreams
For a 7-bit buffer implementation, the results are shown in Table I.
For an 8-bit buffer implementation, the results are shown in Table II.
The system 1700 may include a coding component 1704 that may implement the various coding or encoding methods described in the present document. The coding component 1704 may reduce the average bitrate of video from the input 1702 to the output of the coding component 1704 to produce a coded representation of the video. The coding techniques are therefore sometimes called video compression or video transcoding techniques. The output of the coding component 1704 may be either stored, or transmitted via a communication connected, as represented by the component 1706. The stored or communicated bitstream (or coded) representation of the video received at the input 1702 may be used by the component 1708 for generating pixel values or displayable video that is sent to a display interface 1710. The process of generating user-viewable video from the bitstream representation is sometimes called video decompression. Furthermore, while certain video processing operations are referred to as “coding” operations or tools, it will be appreciated that the coding tools or operations are used at an encoder and corresponding decoding tools or operations that reverse the results of the coding will be performed by a decoder.
Examples of a peripheral bus interface or a display interface may include universal serial bus (USB) or high definition multimedia interface (HDMI) or DisplayPort, and so on. Examples of storage interfaces include serial advanced technology attachment (SATA), peripheral component interface (PCI), integrated drive electronics (IDE) interface, and the like. The embodiments described in the present document may be embodied in various electronic devices such as mobile phones, laptops, smartphones or other devices that are capable of performing digital data processing and/or video display.
Some embodiments of the present document are now presented in clause-based format.
In the present document, the term “video processing” may refer to video encoding, video decoding, video compression or video decompression. For example, video compression algorithms may be applied during conversion from pixel representation of a video to a corresponding bitstream representation or vice versa. The bitstream representation of a current video block may, for example, correspond to bits that are either co-located or spread in different places within the bitstream, as is defined by the syntax. For example, a macroblock may be encoded in terms of transformed and coded error residual values and also using bits in headers and other fields in the bitstream.
From the foregoing, it will be appreciated that specific embodiments of the present disclosure have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the presently disclosed embodiments are not limited except as by the appended claims.
Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing unit” or “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
It is intended that the specification, together with the drawings, be considered exemplary only, where exemplary means an example. As used herein, the use of “or” is intended to include “and/or”, unless the context clearly indicates otherwise.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
| Number | Date | Country | Kind |
|---|---|---|---|
| PCT/CN2019/095504 | Jul 2019 | WO | international |
This application is a continuation of U.S. application Ser. No. 17/978,263, filed on Nov. 1, 2022, which is a continuation of U.S. application Ser. No. 17/570,753, filed on Jan. 7, 2022, which is a continuation of International Application No. PCT/CN2020/100992, filed on Jul. 9, 2020, which claims the priority to and benefits of International Patent Application No. PCT/CN2019/095504, filed on Jul. 10, 2019. For all purposes under the law, the entire disclosures of the aforementioned applications are incorporated by reference as part of the disclosure of this application.
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| Document: JVET-L1001, Bross et al. “Versatile Video Coding {Draft 3),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and 1SO/IEC UTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018. |
| Document: JVET-N1001, Bross et al. “Versatile Video Coding (Draft 5),” Joint Video Experts Team {JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019. |
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| Document: JVET-N0250, Ku et al. “Non-CE8: Reference Memory Reduction for Intra Block Copy,” Joint Video Experts Team (JVET) of ITU-T S, G 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019. |
| Document: JVET-N0251, Ku et al. “Non-CE8: Intra Block Copy Clean-Up,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC UTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019. |
| Document: JVET-N0472, Ku et al. “Non-CEB: On IBC Reference Buffer Design,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and SO/IEC JTC 1/SC 29/WG 1114th Meeting, Geneva, CH, Mar. 19-27, 2019. |
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| Document: JVET-M1001, Bross et al. “Versatile Video Coding (Draft 4),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and 1SO/IEC UTC 1/SC 29/WG 11, 13th Meeting, Marrakech, MA, Jan. 9-18, 2019. |
| Document: JVET-L0159, Nam et al. “Non-CE8: Block Vector Predictor for IBC,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and SO/IEC JTC 1/SC 29/WG 1112th Meeting, Macau, CN, Oct. 8-12, 2018. |
| JCTVC-Q1121—Sole etal. “HEVC Screen Content Coding Core Experiment 1 (SCCE1): Intra Block Copying Extensions,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC1/ SC29/ WG11 17th Meeting, Valencia, ES Mar. 27-Apr. 4, 2014. |
| JCTVC-R0184—Pang et al. “SCCE1: Test 1.1—Intra Block Copy with Different Areas,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and 1SO/IEC JTC1/SC29/WG11 18th Meeting, Sapporo, JP, Jun. 30-Jul. 9, 2014. |
| Document: JVET-N0383, Ku et al. “Non-CE8: IBC Search Range Adjustment for Implementation Consideration,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019. |
| Document: JVET-O0248, Gao et al. “CE8-Related: Dedicated IBC Reference Buffer without Bitstream Restrictions,” Joint Video Experts Team JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019. |
| Document: JVET-O0127, Li et al. “CE8-Related: IBC Modifications,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019. |
| Document: JVET-L0368, Chen et al., “CE4: Affine Merge Enhancement with Simplification (Test 4.2.2),” Joint Video Experts Team (JVET) of ITU WP SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018. |
| Document: JVET-L0404, Van et al. “CE8-Related: Restrictions for the Search Area of the IBC Blocks in CPR,” Joint Video Experts Team JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting: Macao, CN, Oct. 3-12, 2018. |
| Document: JCTVC-O0352, Flynn et al. “BoG Report on Range Extensions Topics,” Joint Collaborative Team on Video Coding (JCT-VG) on ITU-Ir SG 16 WP 3 and ISO/IEC JTC 1/SC 29NvG 11, 15th Meeting, Geneva, CH, Oct. 23-Nov. 1, 2013. |
| Ku et al. “Intra Block Copy in HEVC Screen Content Coding Extensions,” IEEE Journal on Emerging and Selected Tropics in Circuits and Systems, Dec. 2016, 6(4):409-419, XP011636923. |
| Document: JVET-L0297, Ku et al. “CE8-Related: CPR Mode with Local Search Range Optimization,” Joint Video Experts Team (JVET) of ITU-I SG 16 WP 3 and ISO/IEC JTC 1/SC 29NvG 11, 12th Meeting, Macao, CN, 3-12 Oct. 1, 2018. |
| Document: JVET-L1002, Chen et al. “Algorithm Description for Versatlie Video Coding and Test Model 3 (VTM 3),” Joint Video Experts Team JVET) of ITU-T SG 16 WP 3 and 1SO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018. |
| Document: JVET-M1002, Chen et al. “Algorithm Description for Versatile Video Coding and Test Model 4 (VTM 4),” Joint Video Experts Team JVET) of ITU-T SG 16 WP 3 and 1SO/IEC JTC 1/SC 29/WG 11, 13th Meeting, Marrakech, MA Jan. 9-18, 2019. |
| Encoder Decoder + Intra Block Copy + Buffer or Reference Buffer+ Bit Depth or Bit-Depth Google Search, Mar. 22, 2022. |
| Intra Block Copy Library USTPO Query for NPL, Mar. 22, 2022. |
| Document: JVET-V0050, Rapaka et al. “On Storage of Unfiltered and Filtered Current Decoded Pictures,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 22nd Meeting: Geneva, CH, Oct. 15-21, 2015. |
| Document: JVET-M0402, Heng et al. “Non-CE8: Comments on Current Picture Referencing,” Joint Video Experts Team (JVET) of ITU-T SG 16 INP 3 and 1SO/IEC JTC 1/SC 29/WG 1113th Meeting: Marrakech, MA, Jan. 9-18, 2019. |
| Document: JVET-O1171, Gao et al. “Bitstram Conformance with a Virtual IBC Buffer Concept,” Joint Video Experts Team (JVET) of ITU-T SG 6 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019. |
| Document: JVET-O1170, Ku et al. “Bitstream Conformance with a Virtual IBC Buffer Concept,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP3and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019. |
| JVET-O2001—Ve-Hannuksela et al. Versatile Video Coding (Draft 6), Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and SO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE Jul. 3-12, 2019. |
| Document: JVET-P1024, Hannuksela et al. “AHG12: single slice per subpic flag,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 1 16th Meeting: Geneva, CH, Oct. 1-11, 2019. |
| Document: JVET-O1161, Ku et al. “An Implementation of JVET-O0568 based on the IBC Buffer Design of JVET-00127,” Joint Video Experts Weam (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019. |
| Document: JVET-N0384, Ku et al. “Non-CE8: IBC Search Range Increase for Small CTU Size,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 14th Meeting, Geneva, CH, Mar. 19-27, 2019. |
| Document: JVET-M0028-v3, Xu, X., et al., “CE8: Summary Report on Screen Content Coding,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13th Meeting: Marrakesh, MA, Jan. 9-18, 2019, 21 pages. |
| Document: JCTVC-O0183, Li, B., et al., “On Intra BC mode,” Joint Collaborative Team on Video Coding (JCT-VG) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WVG 11 15th Meeting: Geneva, CH, Oct. 23-Nov. 1, 2013, 12 pages. |
| Document: JVET-L1028-v3, Xu, X., et al., “Description of Core Experiment 8: Screen Content Coding Tools,” Joint Video Experts Team {JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 12th Meeting: Macao, CN, Oct. 3-12, 2018, 14 pages. |
| Alshin et al. “RCE3: Intra Block Copy Search Range (Tests A),” Joint Collaborative Team on Video Coding (JCT-VG) of ITU-T SG 16 WP 3 and 1SO/IEC JTC 1/SC 29/WG 1116th Meeting: San Jose, US, Jan. 9-17, 2014, document JCTVC-P0211, 2014. |
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| Number | Date | Country | |
|---|---|---|---|
| 20240056568 A1 | Feb 2024 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17978263 | Nov 2022 | US |
| Child | 18489195 | US | |
| Parent | 17570753 | Jan 2022 | US |
| Child | 17978263 | US | |
| Parent | PCT/CN2020/100992 | Jul 2020 | WO |
| Child | 17570753 | US |
