Sample rate conversion combined with DSM

Abstract

Digital to Analog Conversion and sample conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel DSM design is used to perform sample rate conversion. The DSM may also be used to perform other digital filtering functions, thus providing a single hardware/software technique to perform both functions. The invention includes a method and apparatus for converting input data samples provided at a first sample rate to an analog output signal. Input data samples are converted by a Delta Sigma Modulator (DSM) in a Digital to Analog Converter (DAC) to output data samples, where internal states of the DSM are updated at a second sample rate unequal to the first sample rate. At least one internal state of the DSM s modified to account for the time difference in response to a new input sample arriving at a time different from an update of the internal states of the DSM.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating how traditional sample rate conversion is performed.

FIG. 2 is a spectrum diagram illustrating the resulting data and artifacts produced after upsampling the input digital signal.

FIG. 3 is a spectrum diagram illustrating the resulting data and artifacts produced after upsampling the input digital signal, highlighting the desired data portion of upsampled digital signal.

FIG. 4 is a spectrum diagram illustrating the resulting data after artifacts have been filtered out with a low pass filter.

FIG. 5 is a spectrum diagram illustrating the resulting data after sample rate conversion.

FIG. 6 is a block diagram illustrating a Prior Art technique of sample rate conversion.

FIG. 7 represents the frequency distribution of the input signal Fsi at the input sample rate in the Prior Art technique of FIG. 6.

FIG. 8 illustrates the reconstruction filter response as applied to the interpolated signal in the Prior Art technique of FIG. 6.

FIG. 9 illustrates the action of the decimation filter in the Prior Art technique of FIG. 6.

FIG. 10 illustrates the resultant data F_so at the output sample rate from the Prior Art technique of FIG. 6.

FIG. 11 is a block diagram illustrating the sample rate conversion method of the present invention.

FIG. 12 is a frequency domain diagram illustrating the input data as input into the sample rate conversion method of FIG. 11.

FIG. 13 is a frequency domain diagram illustrating the results of interpolating the input data of FIG. 12 and illustrating the application of the decimation filter to the upsampled signal.

FIG. 14 is a frequency domain diagram illustrating the results of decimating the data of FIG. 13 to produce the sample rate converted data.

FIG. 15 illustrates the frequency response plots of the filter with the unaltered A matrix and with A^1/2

FIG. 16 illustrates a typical scenario of the integration for one state variable update.

FIG. 17 illustrates plots of polynomials for the first four state variables of the 8th-order scaling filter.

FIG. 18 is an overall diagram of the new sample rate conversion method.

FIG. 19 is a block diagram of an 8th-order DSM, which is intended for an audio application with a 20 KHz signal bandwidth at the F_so frequency of 384 KHz.

FIG. 20 illustrates frequency response plots of the STF with the unaltered A matrix and with A^1/2

FIG. 21 is a block diagram of an SRC+PWM module actually built using the DSM shown in FIG. 19.

Claims

1. A method of converting input data samples provided at a first sample rate to an analog output signal, comprising the steps of: converting, by a Delta Sigma Modulator (DSM) in a Digital to Analog Converter (DAC), where internal states of the DSM are updated at a second sample rate unequal to the first sample rate, the input data samples to produce output data samples at the second sample rate;in response to a new input sample arriving at a time different from an update of the internal states of the DSM, modifying at least one internal state of the DSM to account for the time difference; andconverting the output samples to an analog output signal.

2. The method of claim 1, wherein the step of modifying comprises the step of modifying the at least one internal state in response to an amount of time elapsing between when an input data sample arrives and the update of the internal states of the DSM.

3. The method of claim 1, wherein the step of modifying comprises the step of modifying the at least one internal state in response to a difference in input value before the input data sample arrives at a time different from the update of the internal states of the DSM, and the input value after the input data sample arrives at a time different from the update of the internal states of the DSM.

4. The method of claim 1, wherein the input changes value no more than once per update of the internal states of the DSM.

5. The method of claim 1, wherein the DAC further comprises a Pulse Width Modulator (PWM).

6. The method of claim 5 wherein the DSM further comprises a plurality of non-linear correction terms in a modulator feedback.

7. The method of claim 1, wherein the DAC comprises a Multiple Element DAC.

8. The method of claim 7, wherein the Multiple Element DAC further comprises Dynamic Element Matching circuitry.

9. The method of claim 2, wherein the at least one internal state comprises at least one element of vector X, vector X representing current states, vector X′ representing what the states will be at the next point in time, vector U representing an input to the filter, and vector Y representing output of the filter, and matrices A, B′, C, and D determine how the states variables are updated and how outputs are made from the internal states, wherein internal state descriptions are represented as X′=AX+B′U Y=CX+DU X=z−1X′

10. The method of claim 9, wherein the B′ matrix comprises a column matrix whose elements are polynomials of the time difference, wherein the polynomials are of increasing degree.

11. An apparatus of converting input data samples provided at a first sample rate to analog output signals, the apparatus comprising: a Delta Sigma Modulator (DSM) having internal states that are updated at a second sample rate unequal to the first sample rate, filtering the input data samples to produce output data samples at the second sample rate;sample rate conversion compensation circuitry for modifying at least one internal state of the DSM in response to a new input sample arriving at a time differing from the update of the internal states of the DSM, to account for the time difference; anda Digital to Analog Converter (DAC) for converting the output data samples at the second sample rate to an analog output signal.

12. The apparatus of claim 11, wherein the sample rate conversion compensation circuitry modifies the at least one internal state in response to an amount of time elapsing between when an input data sample arrives and updates of the internal states of the DSM.

13. The apparatus of claim 11, wherein the sample rater conversion compensation circuitry modifies the at least one internal state in response to a difference in input value before the input data sample arrives at a time different from the update of the internal states of the DSM, and the input value after the input data sample arrives at a time different from the update of the internal states of the DSM.

14. The apparatus of claim 11, wherein the input changes value no more than once per update of the internal states of the DSM.

15. The apparatus of claim 11, wherein the DAC further comprises a Pulse Width Modulator (PWM).

16. The apparatus of claim 15 wherein the DSM further comprises a plurality of non-linear correction terms in a modulator feedback.

17. The apparatus of claim 11, wherein the DAC comprises a Multiple Element DAC.

18. The apparatus of claim 17, wherein the Multiple Element DAC further comprises Dynamic Element Matching circuitry.

19. The apparatus of claim 12, wherein the at least one internal state comprises at least one element of vector X, vector X representing current states, vector X′ representing what the states will be at the next point in time, vector U representing an input to the filter, and vector Y representing output of the filter, and matrices A, B′, C, and D determine how the states variables are updated and how outputs are made from the internal states, wherein internal state descriptions are represented as X′=AX+B′U Y=CX+DU X=z−1X′

20. The apparatus of claim 19, wherein the B′ matrix comprises a column matrix whose elements are polynomials of the time difference, wherein the polynomials are of increasing degree.