Patent Application
20190238125
Computing systems have made significant contributions toward the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous devices, such as desktop personal computers (PCs), laptop PCs, tablet PCs, netbooks, smart phones, servers, and the like have facilitated increased productivity and reduced costs in communicating and analyzing data in most areas of entertainment, education, business, and science. One common aspect of computing systems is the communication of data within and between computing systems.
Sampling circuits are commonly used in data communication sub-systems. A sampling circuit can sample a voltage level of a signal and hold its value for a period of time. There are applications that require the sampling circuit to have a constant bandwidth across a range of temperatures. However, the bandwidth of conventional sampling circuits can decrease as the operating temperature of the sampling circuit increases. Accordingly, there is a continuing need for improved sampling circuits.
The present technology may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the present technology directed toward a sampling circuit with a substantially temperature insensitive bandwidth. In one embodiment, the sampling circuit can include a source-follower coupled transistor, a hold capacitor, and a clocked sampling transistor. The source-follower coupled transistor can be biased by a temperature dependent current source. A gate of the source-follower coupled transistor can be coupled to an input node of the sampling circuit, and the hold capacitor can be coupled to an output node of the sampling circuit. The cocked sampling transistor can be coupled between a source of the source-follower transistor and the hold capacitor. The source-follower coupled transistor and the clocked sampling transistor can be sized so that a combination of variances in an output impedance of the source-follower coupled transistor and an on-resistance of the clocked sampling transistor is dominated by a variance in a bias current of the temperature dependent current source. In one implementation, the bias current of the temperature dependent current source can be a Proportional-To-Absolute-Temperature (PTAT) current.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Embodiments of the present technology are illustrated by way of example and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Reference will now be made in detail to the embodiments of the present technology, examples of which are illustrated in the accompanying drawings. While the present technology will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it is understood that the present technology may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present technology.
Some embodiments of the present technology which follow are presented in terms of routines, modules, logic blocks, and other symbolic representations of operations on data within one or more electronic devices. The descriptions and representations are the means used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. A routine, module, logic block and/or the like, is herein, and generally, conceived to be a self-consistent sequence of processes or instructions leading to a desired result. The processes are those including physical manipulations of physical quantities. Usually, though not necessarily, these physical manipulations take the form of electric or magnetic signals capable of being stored, transferred, compared and otherwise manipulated in an electronic device. For reasons of convenience, and with reference to common usage, these signals are referred to as data, bits, values, elements, symbols, characters, terms, numbers, strings, and/or the like with reference to embodiments of the present technology.
It should be borne in mind, however, that all of these terms are to be interpreted as referencing physical manipulations and quantities and are merely convenient labels and are to be interpreted further in view of terms commonly used in the art. Unless specifically stated otherwise as apparent from the following discussion, it is understood that through discussions of the present technology, discussions utilizing the terms such as “receiving,” and/or the like, refer to the actions and processes of an electronic device such as an electronic computing device that manipulates and transforms data. The data is represented as physical (e.g., electronic) quantities within the electronic device's logic circuits, registers, memories and/or the like, and is transformed into other data similarly represented as physical quantities within the electronic device.
In this application, the use of the disjunctive is intended to include the conjunctive. The use of definite or indefinite articles is not intended to indicate cardinality. In particular, a reference to “the” object or “a” object is intended to denote also one of a possible plurality of such objects. It is also to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.
Referring to
The source-follower amplifier 110 can produce a signal at the input of the clocked transmission gate 170 from the signal received at the input node 120. The source-follower amplifier 110 can have an output impedance of (1/gm). During an ‘on-state’ of the clock signal 160, the clocked transmission gate 170 can pass the signal at the output of the source-follower amplifier 110 to the storage element 140. During the on state, the clocked transmission gate 170 can have an on-resistance of Ron. During the ‘off-state’ of the clock signal 160, the storage element 140 can hold the output node 150 at the signal level of the signal passed by the clocked transmission gate 170. In an exemplary implementation, the input node 120 can vary between a first signal level Vin+ and a second signal level Vin−. When the signal at the input node 120 is at a voltage level of Vin+, the source-follower amplifier 110 can produce a signal having a voltage level of approximately Vin+ at the input to the clocked transmission gate 170. During a high state of a clock signal 160, the clocked transmission gate 170 can pass the voltage level of approximately Vin+ to the storage element 140 and drive the output node 150 to the voltage level of approximately Vin+. When the clock signal 160 switches to a low state, the storage element 140 can maintain the output node 150 at the voltage level of approximately Vin+. When the signal at the input node 120 transitions to a voltage level of Vin−, the source-follower amplifier 110 can produce a signal having a voltage level of approximately Vin− at the input to the clocked transmission gate 170. During another high state of the clock signal 160, the clocked transmission gate 170 can pass the voltage level of approximately Vin− to the storage element 140 and drive the output node 150 to the voltage level of approximately Vin−. When the clock signal 160 switches to a low state, the storage element 140 can maintain the output node 150 at the voltage level of approximately Vin−.
In aspects, the bias current of the temperature dependent current source 130 supplied to the source-follower amplifier 110 can vary as a function of the temperature of the sampling circuit 100. In addition, the sampling circuit 100 can be characterized by a time constant (τ) that is a function of an output impedance (1/gm) of the source-follower amplifier 110, an on-resistance (Ron) of the clocked transmission gate 170, and a capacitance (C) of the storage element 140. The output impedance (1/gm) of the source-follower amplifier 110 and on-resistance (Ron) of the clocked transmission gate 170 can vary with the operating temperature of the sampling circuit 100. The temperature variance in the output impedance (1/gm) of the source-follower amplifier 110 and on-resistance (Ron) of the clocked transmission gate 170 can be determined by one or more manufacturing parameters. In such case, a variance in the time constant (τ) of the sampling circuit 100 can be substantially cancelled by the temperature variance in the bias current from the temperature dependent current source 130. Therefore, by manufacturing the source-follower amplifier 110 and the clocked transmission gate 170 according to one or more specified manufacturing parameters that variance in the gain of the source-follower amplifier 110 and the variance in the on-resistance of the clocked transmission gate 170 can cancel each other out in the bandwidth of the sampling circuit 100. In such case, the bandwidth of the sampling circuit 100 can be substantially insensitive to variations in the operating temperature of the sampling circuit 100.
Referring now to
A gate of the source-follower coupled transistor 210 can be coupled to an input node 250. A drain of the source-follower coupled transistor 210 can be coupled to a first supply potential (Vdd). The source-follower coupled transistor 210 can also be biased by the temperature dependent current source 220 coupled to a source of the source-follower coupled transistor 210. A gate of the clocked sampling transistor 230 can be coupled to a clock signal. A source of the clocked sampling transistor 230 can be coupled to the source of the source-follower coupled transistor 210. A drain of the clocked sampling transistor 230 can be coupled to an output node 260. The hold capacitor 240 can be coupled between the output node 260 and a second supply potential (VSS). The source-follower transistor 210 and the clocked sampling transistor 230 can be n-type enhancement mode Metal Oxide Semiconductor Field Effect Transistors (MOSFET). The temperature dependent current source 220 can be a Proportional-To-Absolute (PTAT) current source.
In an exemplary implementation, the input node 250 can vary between a first signal level Vin+ and a second signal level Vin−. When the signal at the input node 250 is at a voltage level of Vin+, the source-follower coupled transistor 210 can produce a signal having a voltage level of Vin+−VGS at the input to the clocked transmission gate 170. During a high state of a clock signal 160, the clocked transmission gate 170 can pass a voltage level of Vin+−VGS−VTH to the storage element 140 and drive the output node 150 to the voltage level of Vin+−VGS−VTH. When the clock signal 160 switches to a low state, the storage element 140 can maintain the output node 150 at the voltage level of approximately Vin+−VGS−VTH. When the signal at the input node 120 transitions to a voltage level of Vin−, the source-follower amplifier 110 can produce a signal having a voltage level of Vin−−VGS at the input to the clocked transmission gate 170. During another high state of the clock signal 160, the clocked transmission gate 170 can pass a voltage level of Vin−−VGS−VTH to the storage element 140 and drive the output node 150 to the voltage level of approximately Vin−−VGS−VTH. When the clock signal 160 switches to a low state, the storage element 140 can maintain the output node 150 at the voltage level of approximately Vin−−VGS−VTH.
The bandwidth of the sampling circuit 200 can be determined as a function of the output impedance (1/gm) of the source-follower coupled transistor 210, the on-resistance (Ron) of the clocked sampling transistor 230, and the capacitance of the hold capacitor 240. The output impedance (1/gm) of the source-follower coupled transistor 210 is provided in Equation 1, and the on-resistance (Ron) of the clocked sampling transistor 230 in Equation 2, as follows.
Wherein β is the gain, VGS is the gate-to-source voltage, VTH is the threshold voltage, and Ib is the bias current of the source-follower coupled transistor 210. Generally, when the temperature (T) increases, the gain (β) and the threshold voltage (VTH) of the source-follower coupled transistor 210 decrease. Therefore, if the bias current (Ib) of the source-follower transistor 210 is constant, both the output impedance (1/gm) of the source-follower coupled transistor 210 and the on-resistance (Ron) of the clocked sampling transistor 230 increases with temperature (T). When the output impedance (1/gm) of the source-follower coupled transistor 210 and the on-resistance (Ron) of the clocked sampling transistor 230 increases with temperature (T), the bandwidth of the sampling circuit 200 decreases. However, if the source-follower coupled transistor 210 is biased with a current source that varies proportional to the operating temperature of the sampling circuit 200 the variance in the output impedance (1/gm) can be dominated by the bias current (Ib) rather than the gain (β). Therefore, sizing the source-follower coupled transistor 210 and the clocked sampling transistor 230 can be utilized to have variations in the output impedance (I/gm) of the source-follower coupled transistor 210 and the on-resistance (Ron) of the clocked sampling transistor 230 with temperature (T) cancel each other.
Referring now to
An inverting input terminal of the operational amplifier 310 can be coupled to a constant voltage source such as a bandgap reference voltage (VBG). The bandgap reference voltage (VBG) is substantially constant as a function of temperature (T). An output terminal of the operational amplifier can be coupled to a gate of the first transistor 320. A drain of the first transistor can be coupled to a first supply potential (Vdd). A source of the first transistor 320 can be coupled to the inverting input terminal of the operational amplifier 310 and a first terminal of the resistor 330. The second terminal of the resistor 330 can be coupled to an emitter of the second transistor 340. A base and a collector of the second transistor can be coupled to a second supply potential (VSS).
During a steady state condition, the operational amplifier 310 can drive the gate of the first transistor 310 so that a potential of VBG is generated at the source of the first transistor 320 and the non-inverting input terminal of the operational amplifier 310. The potential of VBG at the source of the first transistor 320 can also cause the second transistor 340 to turn on and conduct current between the emitter and collector of the second transistor 340. The voltage generated by the operational amplifier 310 at the gates of the first and third transistors 320, 350 can be approximately the sum of the bandgap reference voltage (VBG) and the threshold voltage (VTH) of the first transistor 320. The threshold voltage (VTH) is the voltage at which the first and second transistors 320, 350 will turn on and conduct current. The voltage generated by the operational amplifier 310 at the gates of the first and third transistors 320, 350 can cause substantially the same current that flows through the first transistor 320 to also flow through the second transistors 350. However, the current flowing through the first and third transistors 320, 350 will decrease as a function of an increase in the operating temperature of the first and third transistors 320, 350. Therefore, the current flowing from the output of the temperature dependent current source can be proportional to the operational temperate. In one implementation, the current can be a Proportional-to-Absolute-Temperature (PTAT) current.
The exemplary temperature dependent current source of
Referring now to
The temperature dependent current source sub-circuit can be a Proportional-To-Absolute (PTAT) current source including an operation amplifier 310, a first transistor 320, a resistor 330, a second transistor 340, and a third transistor 350. The current source can generate a PTAT current (IPAT) that decreases as a function of increases in the operating temperature as described above with respect to
The current mirror sub-circuit can include fourth and fifth transistors 410, 420. The fifth transistor 420 provides a bias current to the sampling sub-circuit that is substantially equal to the PTAT current (IPTAT) flowing through the fourth transistor 410. Therefore, the bias current provided to the sampling sub-circuit will be the PTAT current (IPTAT) that decreases as a function of increases in the operating temperature.
The sampling sub-circuit can include sixth and seventh transistors 210, 230 and a hold capacitor 240. The sampling sub-circuit can sample an input signal to generate an output signal with a substantially temperature insensitive bandwidth as described above with respect to
Referring now to
The foregoing descriptions of specific embodiments of the present technology have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, to thereby enable others skilled in the art to best utilize the present technology and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
This Application claims the benefit of U.S. Patent Provisional Application No. 62/623,435 filed Jan. 29, 2018, which is incorporated herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62623435 | Jan 2018 | US |
