Claims
- 1. A sampling frequency converter comprising:
- oversampling means for oversampling an input sample train;
- a memory;
- write control means for writing oversampled data provided from said oversampling means in said memory with a clock synchronized with the oversampled data;
- sampling frequency ratio measuring means for measuring a frequency ratio of a sampling frequency of the input sample train and a sampling frequency of an output sample train to be output;
- read control means for reading from said memory the oversampled data used for obtaining interpolation data at two points before and after an output sample value which realizes the measured sampling frequency ratio by a polynomial interpolation;
- polynomial interpolation means for obtaining the interpolation data at the two points by the polynomial interpolation on the basis of the oversampled data read from said memory by said read control means; and
- linear interpolation means for linear-interpolating between the polynomial interpolation data at the two points obtained by the polynomial interpolation and thereby obtaining the output sample value realizing the sampling frequency ratio.
- 2. A sampling frequency converter as defined in claim 1 where in said sampling frequency ratio measuring means comprises a counter counting with a clock synchronized with the input sample train and providing a count of said counter for plural word periods of the output sample train as said sampling frequency ratio;
- said read control means uses, as read address data for reading said memory, high order data among three data obtained by dividing bits which are an accumulated value of counts of said counter accumulated for each output sample period;
- said polynomial interpolation means uses, as address data for reading a second memory storing an interpolation coefficient for effecting the polynomial interpolation, middle order data among the three data obtained by dividing the bits which are the accumulated value of the counts of said counter; and
- said linear interpolation means uses, as coefficient data for the linear interpolation, low order data among the three data obtained by dividing the bits which are the accumulated value of the counts of said counter.
- 3. A sampling frequency converter comprising:
- a memory;
- sampling frequency ratio measuring means for measuring a frequency ratio of a sampling frequency of an input sample train and a sampling frequency of an output sample train to be output;
- read control means for reading from said memory an input sample necessary for obtaining an output sample value which realizes the measured sampling frequency ratio by interpolation on the basis of the sampling frequency ratio; and
- interpolation means for obtaining the output sample data by interpolation on the basis of the input sample data read from said memory by said read control means;
- said sampling frequency ratio measuring means comprising:
- a counter counting a clock synchronized with the input sample; and
- count output means for measuring a count of said counter for plural word periods of the output sample and outputting this count as a measured value of the sampling frequency ratio.
- 4. A sampling frequency converter as defined in claim 3 wherein said sampling frequency ratio measuring means comprises:
- sampling frequency ratio variation detection means for detecting variation in the measured sampling frequency ratio; and
- sampling frequency ratio measuring period control means for prolonging the plural word periods of the output sample during which the sampling frequency ratio is measured when variation in the sampling frequency ratio is small and shortening the plural word periods of the output sample when variation in the sampling frequency ratio is large.
- 5. A sampling frequency converter as defined in claim 3 wherein said read control means comprises:
- address difference detection means for detecting difference between a write address and a read address for said memory; and
- read address correction means for correcting, upon detection of approaching of the read address within a predetermined range toward the write address on the basis of the detected address difference, the read address in a direction in which the read address is withdrawn from the write address.
Priority Claims (2)
Number |
Date |
Country |
Kind |
4-061193 |
Feb 1992 |
JPX |
|
4-088113 |
Mar 1992 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 08/018,995, filed Feb. 17, 1993, now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (6)
Number |
Date |
Country |
61-204700 |
Sep 1986 |
JPX |
62-101112 |
May 1987 |
JPX |
63-296511 |
Dec 1988 |
JPX |
1-175311 |
Jul 1989 |
JPX |
2-21712 |
Jan 1990 |
JPX |
2-21714 |
Jan 1990 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
18955 |
Feb 1993 |
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