Claims
- 1. A method for generating clock signals for use in activating and deactivating rotating capacitors in a receiver mixer with a plurality of signal paths to sample a received data signal, the method comprising:
producing a reference signal; generating a set of clock signals from the reference signal; and distributing the set of clock signals to the plurality of signal paths, wherein the set of clock signals are used to activate and deactivate rotating capacitors in each of the signal paths.
- 2. The method of claim 1, wherein the set of clock signals are also used to activate and deactivate a bank of rotating capacitors.
- 3. The method of claim 1, wherein the set of clock signals are also used to reset and precharge rotating capacitors in each of the signal paths.
- 4. The method of claim 1, wherein the producing step comprises using a local oscillator (LO) to produce the reference signal.
- 5. The method of claim 4, wherein the reference signal approximately equals the carrier frequency of the received data stream.
- 6. The method of claim 1, wherein the generating step comprising:
producing a clock signal by dividing the reference signal by an integer amount, N; and providing the clock signal to a signal generator.
- 7. The method of claim 6, wherein the signal generator is a sequence of registers forming a circular shift register.
- 8. The method of claim 7, wherein the set of clock signal comprises the outputs of each of the registers in the circular shift register.
- 9. The method of claim 6, wherein the signal generator is an N-register circular shift register.
- 10. The method of claim 9, wherein N is eight.
- 11. The method of claim 9, wherein all N registers are initially set to zero and a one value is loaded into one register out of the N registers.
- 12. The method of claim 1, wherein the distributing step comprises placing the set of clock signals onto a set of connections connected to each signal path in the plurality of signal paths.
- 13. The method of claim 12, wherein each signal path receives the set of clock signals.
- 14. The method of claim 12, wherein each signal path receives the same set of clock signals.
- 15. The method of claim 1, wherein the distributing step comprises:
inserting a delay between transitions in the signals in the set of clock signals; and placing the set of clock signals onto a set of connections connected to each signal path in the plurality of signal paths.
- 16. A circuit for generating a set of clock signals for use in activating and deactivating rotating capacitors in a radio receiver with a plurality of signal paths, the circuit comprising:
a reference signal generator to generate a clock signal at a specified frequency; a clock divider coupled to the reference signal generator, the divider containing circuitry to divide the clock signal to change the frequency of the clock signal; and a clock generator coupled to the clock divider, the clock generator containing circuitry to output the set of clock signals to the plurality of signal paths.
- 17. The circuit of claim 16, wherein the clock generator comprises a sequence of registers, and an output of one register is coupled to an input of another register, forming a circular ring of registers.
- 18. The circuit of claim 17, wherein there are N registers in the clock generator.
- 19. The circuit of claim 18, wherein N is eight.
- 20. The circuit of claim 16, wherein the reference signal generator is a local oscillator.
- 21. The circuit of claim 20, wherein each signal path is coupled to the local oscillator.
- 22. The circuit of claim 16, wherein the clock divider divides the clock signal by an integer value, N.
- 23. The circuit of claim 16, wherein the plurality of signal paths form an orthogonal bases.
- 24. The circuit of claim 23, wherein there are four signal paths: in-phase plus (I+) and minus (I−) and quadrature-phase plus (Q+) and minus (Q−).
- 25. The circuit of claim 16, wherein the plurality of signal paths form a non-orthogonal bases.
- 26. The circuit of claim 16, wherein each signal path is clocked by a signal clock provided by the reference signal generator.
- 27. The circuit of claim 26, wherein each signal path's clock differs from other signal path's clocks.
- 28. The circuit of claim 16, wherein the clock generator has a plurality of outputs, and the circuit further comprises a non-overlap circuit with inputs coupled to the clock generator and outputs provided to the plurality of signal paths, the non-overlap circuit containing circuitry to insert a delay between signal transitions in the outputs of the clock generator.
- 29. The circuit of claim 28, wherein the non-overlap circuit comprises a sequence of N logic units, wherein an output of one logic unit is coupled to a first input of another logic unit, forming a circular ring of logic units, each logic unit has a second input coupled to an output of the clock generator, and each logic unit is a combinatorial circuit.
- 30. The circuit of claim 29, wherein each logic unit comprises:
a two-input AND gate; and an inversion gate coupled to a first input of the two-input AND gate.
- 31. A radio receiver comprising:
an radio frequency (RF) input to receive RF signals; a current-mode sampling mixer coupled to the RF input, the mixer comprising:
a plurality of signal paths, each signal path coupled to the RF input and a local oscillator, the signal path containing circuitry to sample a received signal provided by the RF input and to output a discrete-time sample stream; a timing circuit coupled to the plurality of signal paths, the timing circuit containing circuitry to control the operation of the signal paths; and a signal processing circuit coupled to the mixer, the signal processing circuit containing circuitry to transform output produced by the plurality of signal paths into user usable data.
- 32. The radio receiver of claim 31 further comprising a quantizer having an input coupled to the mixer and an output coupled to the signal processing circuit, the quantizer containing circuitry to convert the discrete-time sample stream into a digital sample stream.
- 33. The radio receiver of claim 31, wherein the signal processing circuit is a digital signal processing circuit.
- 34. The radio receiver of claim 31, wherein each signal path is coupled to its own local oscillator.
- 35. The radio receiver of claim 31, wherein each signal path is coupled to a single local oscillator.
- 36. The radio receiver of claim 31, wherein each of the signal paths uses rotating capacitors to sample the received signal, and the timing circuit comprising:
a reference signal generator to generate a clock signal at a specified frequency; a clock divider coupled to the reference signal generator, the divider containing circuitry to divide the clock signal by a specified integer number, N; and a clock generator coupled to the clock divider, the clock generator containing circuitry to output the set of clock signals to the plurality of signal paths.
- 37. The radio receiver of claim 36, wherein the received signal is converted into a received current by a transconductance amplifier, and rotating capacitors integrate the received current to sample the received signal.
- 38. The radio receiver of claim 36, wherein there are N rotating capacitors for each signal path.
- 39. The radio receiver of claim 38, wherein the N rotating capacitors are partitioned into at least two banks of rotating capacitors.
- 40. The radio receiver of claim 39, wherein there are two banks of rotating capacitors with N/2 rotating capacitors in each bank.
- 41. The radio receiver of claim 36, wherein the current-mode sampling mixer further comprising a history capacitor coupled to the RF input and to the plurality of signal paths, the history capacitor to sample the received signal.
- 42. The radio receiver of claim 41, wherein the ratio of history capacitor and rotating capacitor capacitance is about 30.
- 43. The radio receiver of claim 41, wherein the ratio of history capacitor to rotating capacitor capacitance is greater than 30.
- 44. The radio receiver of claim 41, wherein the history capacitor continuously samples the received signal and each rotating capacitor samples only a portion of the received signal.
- 45. The radio receiver of claim 44, wherein one rotating capacitor in each signal path is active at any given time.
- 46. The radio receiver of claim 36, wherein the clock generator comprises a sequence of registers, and an output of one register is coupled to an input of another register, forming a circular ring of registers.
- 47. The radio receiver of claim 46, wherein there are N registers in the clock generator.
- 48. The radio receiver of claim 31, wherein the radio transceiver operates in a Bluetooth compliant communications network.
- 49. The radio receiver of claim 31, wherein the radio transceiver operates in a cellular based communications network.
- 50. A wireless communications device comprising:
an antenna to receive and transmit radio frequency (RF) signals; a RF receiver coupled to the antenna, the RF receiver containing circuitry to convert RF signals into a data stream, the RF receiver comprising a current-mode sampling mixer, the current-mode sampling mixer comprising:
a plurality of signal paths, each signal path coupled to the antenna and a local oscillator, the signal path containing circuitry to sample a received signal provided by the antenna and produce a discrete-time sample stream of the received signal; a timing circuit coupled to the plurality of signal paths, the timing circuit containing circuitry to control the operation of the signal paths; a digital baseband (DBB) controller coupled to the RF transceiver, the DBB controller containing circuitry to digitally process the data stream provided by the RF transceiver and convert it into user usable data; and a memory coupled to the DBB controller, the memory containing storage elements to store data and programs.
- 51. The wireless communications device of claim 50 further comprising a quantizer having an input coupled to the RF receiver and an output coupled to the DBB controller, the quantizer containing circuitry to convert the data stream into a digital data stream.
- 52. The wireless communications device of claim 50 further comprising an analog-to-digital converter (ADC) having an input coupled to the RF receiver and an output coupled to the DBB controller, the ADC containing circuitry to convert the data stream into the digital data stream.
- 53. The wireless communications device of claim 50, wherein the DBB controller decodes, and error detects and corrects the digital data stream.
- 54. The wireless communications device of claim 50, wherein the DBB controller further comprises a communications protocol software stack along with applications.
- 55. The wireless communications device of claim 50 operates in a Bluetooth compliant communications network.
- 56. The wireless communications device of claim 50 operates in a cellular based communications network.
Parent Case Info
[0001] This application claims priority to the provisional application entitled “A Current Steering Approach for Placing Two Zeros on Folded-Over Frequencies in Decimating FIR Filters”, filed Oct. 26, 2001, serial No. 60/348,902, which provisional application is incorporated herein by reference.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60348902 |
Oct 2001 |
US |