SAMPLING TIMING MONITORING SYSTEM AND ENDOSCOPE HAVING THE SAME

Abstract

There is provided a sampling timing monitoring system, which includes at least one abnormal state detection circuit. The at least one abnormal state detection circuit includes a pulse generation circuit that generates a pulse having a pulse width corresponding to a relationship between timing of a driving signal for driving an image pickup device and timing of a sampling signal to be supplied to a sampling circuit carrying out correlated double sampling for an analog output signal outputted by the image pickup device, and a detection circuit that detects an abnormal state of the timing of the sampling signal with respect to the timing of the driving signal in accordance with the pulse width of the pulse generated by the pulse generation circuit.

Description

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

FIG. 1 is a block diagram of an electronic endoscope according to a first embodiment of the invention.

FIGS. 2A, 2B, 2C, 2D and 2E respectively illustrate timing charts for a horizontal driving signal, a reset gate signal, an analog output signal, a black sampling signal, and an image sampling signal.

FIGS. 2F and 2G respectively illustrate timing charts of an output signal of a flip-flop of a detection circuit for a black sampling signal, and an output signal of a flip-flop of a detection circuit for an image sampling signal.

FIG. 3 is a circuit diagram of an abnormal state detection circuit provided in a programmable IC according to the first embodiment.

FIG. 4 shows a truth table of a flip-flop provided in the abnormal state detection circuit.

FIG. 5 is a circuit diagram of an abnormal state detection circuit provided in a programmable IC according to a second embodiment.

FIGS. 6A, 6B, 6C and 6D show examples of signals generated in the abnormal state detection circuit shown in FIG. 5 when driving and sampling signals in a normal state are inputted to the abnormal state detection circuit.

FIGS. 7A, 7B, 7C, 7D and 7E are timing charts respectively illustrating a horizontal driving signal, a reset gate signal, an analog output signal, a black sampling signal, and an image sampling signal, for explaining a case where each of the black sampling signal and the image sampling signal is in an abnormal state.

FIGS. 8A, 8B, 8C and SD show examples of signals generated in the abnormal state detection circuit shown in FIG. 5 when the driving and sampling signals in the abnormal state shown in FIGS. 7A to 7E are inputted to the abnormal state detection circuit.

FIG. 9 is a circuit diagram illustrating an example of the driving signal state detection circuit.

Claims

1. A sampling timing monitoring system, comprising: at least one abnormal state detection circuit including:a pulse generation circuit that generates a pulse having a pulse width corresponding to a relationship between timing of a driving signal for driving an image pickup device and timing of a sampling signal to be supplied to a sampling circuit carrying out correlated double sampling for an analog output signal outputted by the image pickup device; anda detection circuit that detects an abnormal state of the timing of the sampling signal with respect to the timing of the driving signal in accordance with the pulse width of the pulse generated by the pulse generation circuit.

2. The sampling timing monitoring system according to claim 1, wherein the detection circuit includes:a counter that obtains a value corresponding to the pulse width of the pulse generated by the pulse generation circuit; anda judgment circuit that judges whether the value obtained by the counter is within a predetermined range,wherein the detection circuit detects the abnormal state of the timing of the sampling signal in accordance with a judgment result of the judgment circuit.

3. The sampling timing monitoring system according to claim 2, wherein the detection circuit judges that the timing of the sampling signal is in the abnormal state if the judgment circuit judges that the value obtained by the counter is not within the predetermined range, and judges that the timing of the sampling signal is in a normal state if the judgment circuit judges that the value obtained by the counter is within the predetermined range.

4. The sampling timing monitoring system according to claim 1, wherein the detection circuit includes:an integrator circuit that integrates the pulse generated by the pulse generation circuit; anda voltage comparator that judges whether an output voltage of the integrator circuit satisfies a predetermined condition,wherein the detection circuit detects the abnormal state of the timing of the sampling signal in accordance with a judgment result of the voltage comparator.

5. The sampling timing monitoring system according to claim 4, wherein the predetermined condition is a predetermined upper voltage,wherein the detection circuit judges that the timing of the sampling signal is in the abnormal state if the voltage comparator judges that the output voltage of the integrator is larger than the predetermined upper voltage, and judges that the timing of the sampling signal is in a normal state if the voltage comparator judges that the output voltage of the integrator is lower than or equal to the predetermined upper voltage.

6. The sampling timing monitoring system according to claim 1, wherein the pulse width of the pulse generated by the pulse generation circuit corresponds to a period from falling of the driving signal to rising of the sampling signal.

7. The sampling timing monitoring system according to claim 1, wherein: the at least one abnormal state detection circuit comprises two abnormal state detection circuits each of which includes the pulse generation circuit and the detection circuit;the driving signal of a first abnormal state detection circuit of the two abnormal state detection circuits is a reset gate signal, and the sampling signal of the first abnormal state detection circuit is a first sampling signal for sampling a part of the analog output signal corresponding to a feedthrough period; andthe driving signal of a second abnormal state detection circuit of the two abnormal state detection circuits is a horizontal driving signal, and the sampling signal of the second abnormal state detection circuit is a second sampling signal for sampling a part of the analog output signal corresponding to an image signal period.

8. The sampling timing monitoring system according to claim 1, further comprising an abnormal state indication unit configured to indicate the abnormal state of the timing of the sampling signal if the abnormal state of the timing of the sampling signal is detected by the detection unit.

9. The sampling timing monitoring system according to claim 8, wherein: the at least one abnormal state detection circuit comprises two abnormal state detection circuits each of which includes the pulse generation circuit and the detection circuit; andthe abnormal state indication unit indicates the abnormal state of the timing of the sampling signal if the abnormal state of the timing of the sampling signal is detected by at least one of the two abnormal state detection circuits.

10. The sampling timing monitoring system according to claim 8, wherein the abnormal state indication unit indicates the abnormal state by emission of light.

11. The sampling timing monitoring system according to claim 1, wherein the pulse generation circuit includes a D-flip-flop having a reset input terminal; andthe driving signal is inputted to a clock input terminal of the D-flip-flop, and the sampling signal is inputted to the reset input terminal of the D-flip-flop.

12. The sampling timing monitoring system according to claim 1, further comprising a programmable integrated circuit which incorporates the at least one abnormal state detection circuit.

13. The sampling timing monitoring system according to claim 1, wherein the at least one abnormal state detection circuit comprises two abnormal state detection circuits each of which includes the pulse generation circuit and the detection circuit,wherein a first driving signal is inputted to a first abnormal state detection circuit of the two abnormal state detection circuits as the driving signal of the first abnormal state detection circuit, and a second driving signal is inputted to a second abnormal state detection circuit of the two abnormal state detection circuits as the driving signal of the second abnormal state detection circuit, andwherein the sampling timing monitoring system further comprises:a driving signal state detection circuit configured to detect an abnormal state of a time difference between the first and second driving signals.

14. The sampling timing monitoring system according to claim 1, wherein: the first driving signal is a reset gate signal and the second driving signal is a horizontal driving signal; andthe driving signal state detection circuit detects the abnormal state of the time difference between the reset gate signal and the horizontal driving signal by judging whether timing of rising of the reset gate signal and timing of rising of the horizontal driving signal coincide with each other.

15. An endoscope, comprising: an image pickup device that outputs an analog output signal corresponding to an image of a subject;a sampling circuit that carries out correlated double sampling for the analog output signal outputted by the image pickup device; andat least one abnormal state detection circuit including:a pulse generation circuit that generates a pulse having a pulse width corresponding to a relationship between timing of a driving signal for driving the image pickup device and timing of a sampling signal to be supplied to the sampling circuit; anda detection circuit that detects an abnormal state of the timing of the sampling signal with respect to the timing of the driving signal in accordance with the pulse width of the pulse generated by the pulse generation circuit.

16. The endoscope according to claim 15, wherein the detection circuit includes:a counter that obtains a value corresponding to the pulse width of the pulse generated by the pulse generation circuit; anda judgment circuit that judges whether the value obtained by the counter is within a predetermined range,wherein the detection circuit detects the abnormal state of the timing of the sampling signal in accordance with a judgment result of the judgment circuit.

17. The endoscope according to claim 15, wherein the detection circuit includes:an integrator circuit that integrates the pulse generated by the pulse generation circuit; anda voltage comparator that judges whether an output voltage of the integrator circuit satisfies a predetermined condition,wherein the detection circuit detects the abnormal state of the timing of the sampling signal in accordance with a judgment result of the voltage comparator.