NSF Award
0539139
This SBIR Phase I project proposes chip-to-chip interconnects that can be applied in the mother boards/ backplanes of high performance networking systems and/or computing systems, where 10 Gb/s and beyond signal speed per channel (serial) is necessary. An innovative cost-effective high speed (> 20Gb/s per channel) electrical interconnect technology, which can increase the signal carrying capacity of the board-level interconnects more than 6 times than the conventional technology is proposed. This can help to route the signal longer distances (at given signal-speed) at lower cost by using standard dielectric material. The company will investigate the design, feasibility of the concept, process development, and data analysis approaches in order to create a high speed interconnect PCB board, and each can carry the signal as high as 20 Gb/s.<br/><br/>The proposed high speed electrical chip-to-chip interconnects will have applications in high speed PCs, high-speed servers, networking systems, gaming machines, communications systems, imaging and video systems.
