SBIR Phase I: Integrated Reactor Scale and Topography Feature Scale Simulator for Plasma Enhanced Semiconductor Processes

Information

  • NSF Award
  • 9960600
Owner
  • Award Id
    9960600
  • Award Effective Date
    1/1/2000 - 24 years ago
  • Award Expiration Date
    6/30/2000 - 23 years ago
  • Award Amount
    $ 99,947.00
  • Award Instrument
    Standard Grant

SBIR Phase I: Integrated Reactor Scale and Topography Feature Scale Simulator for Plasma Enhanced Semiconductor Processes

This Small Business Innovation Research Phase I project will develop a statistical (Monte Carlo) software model and software simulation tool for the pre-sheath and sheath regions of low pressure plasmas used in IC fabrication. The objective is to bridge the time/length scales between reactor scale phenomena and feature scale phenomena. The sheath models will be integrated with an existing reactor scale software model (CFD-ACE+) and feature scale software simulators (SPEEDIE and CATS). The work will fill a void currently faced by designers of plasma equipment and processes. It will evaluate the influence of macroscopic reactor conditions on feature scale profile evolution. Stanford University Center for Integrated Circuits will be a sub-contractor on this project. The Phase I effort will focus on an intermediate-scale model based on kinetic treatment of charged particle transport near the wafer surface. This model will be an interface between a hydrodynamic model in CFD-ACE+ and collisionless gas phase models in SPEEDIE and CATS for interstructure particle transport. The plasma-presheath model will provide spatially resolved distributions of ion flux, energy and angular distributions to SPEEDIE and CATS. Both SPEEDIE and CATS require die level models to resolve the impact of circuit layout/topography on species generation/loss, charged particle collection and currents paths to the substrate.<br/><br/>In Phase II, the models will be refined and validated (against experiments conducted at Stanford) for silicon etch processes in Cl2 and SF6 systems. CATS will be expanded to include the wafer charging circuit and will be merged with SPEEDIE. The commercial availability of the capability will allow process engineers to design better processes and identify equipment/process deficiencies before physical prototyping. The use of the model will enable the reduction of potential yield losses due to unsatisfactory gap/step coverage, film noncomformality and undesirable etch profiles. According to industry observers, even a 2% improvement in the fabrication yield will provide significant savings to the industry.

  • Program Officer
    Jean C. Bonney
  • Min Amd Letter Date
    11/29/1999 - 24 years ago
  • Max Amd Letter Date
    11/29/1999 - 24 years ago
  • ARRA Amount

Institutions

  • Name
    CFD RESEARCH CORPORATION
  • City
    HUNTSVILLE
  • State
    AL
  • Country
    United States
  • Address
    701 McMillian Way NW, Suite D
  • Postal Code
    358062923
  • Phone Number
    2567264800

Investigators

  • First Name
    Phillip
  • Last Name
    Stout
  • Email Address
    pjs@cfdrc.com
  • Start Date
    11/29/1999 12:00:00 AM

FOA Information

  • Name
    Industrial Technology
  • Code
    308000

Program Element

  • Text
    SMALL BUSINESS PHASE I
  • Code
    5371

Program Reference

  • Text
    SMALL BUSINESS PHASE I
  • Code
    5371
  • Text
    MANUFACTURING BASE RESEARCH
  • Code
    9146
  • Text
    MANUFACTURING