NSF Award
0319170
This Small Business Innovation Research (SBIR) Phase I project will develop a novel, non-contact/stress-free polishing method for planarization of copper (Cu)/low-k (dielectric constant) interconnects required for the fabrication of nanochip integrated circuits (IC). A currently used process step, chemical-mechanical-polishing (CMP), is adequate for copper/silicon dioxide interconnects. However, the reduced mechanical strength of the low-k dielectric materials required for nanochips (100nm and smaller interconnects) renders CMP incompatible with future IC interconnects. The proposed method utilizes pulsed electrolysis to effect complete electrochemical removal of copper overplate beginning from the center of the wafer and moving outward where electrical contact is provided. The Phase I research issues include: 1) complete removal of copper overplate, i.e. no copper islands remaining, and 2) no damage to the interconnect, i.e. filled and not eroded or dished. Real-time video feed observation and post process FIB-SEM analysis will be conducted to validate process feasibility. Analytical work will be conducted to establish a theoretical basis for the proposed electrochemical process.<br/><br/>Commercially, the non-contact/stress-free polishing method will find application to Cu/low-k interconnects required for integrated circuits down to the 35nm mode. Additional applications of the process include micro-electro-mechanical systems (MEMS) and nano-electro-mechanical systems (NEMS). The industry addressed semiconductor is an important aspect of the US commercial economy. The result of the research will lead to a marketable manufacturing process/manufacturing tool in the form of an electrochemical module incorporating the non-contact/zero stress polishing process.
