NSF Award
0611150
This Small Business Innovation Research (SBIR) Phase I project will investigate the technical and commercial feasibility of a general-purpose platform for reconfigurable computing. The intellectual merit of the effort is justified by the creation of essential elements for a computing environment needed to sustain a mainstream reconfigurable platform. These elements include the development of a reference design and requisite software for a tightly integrated platform. Reconfigurable computing through Field Programmable Gate Arrays (FPGAs) provides faster, smaller and lower power IT solutions. Trends and scaling laws project continuing advances in this technology that outpace the traditional microprocessor. Adoption has been limited mainly due to the complexity of the programming environment and the limitations of a loosely coupled co-processor implementation. The research objectives of the Phase I effort are to create and adapt software products that target a proxy hardware development board hosting a reconfigurable chip with a tightly coupled embedded processor. The anticipated results are an assessment of technical and performance issues of the integrated system.<br/><br/>The broader impacts of the proposed activity include the potential commercial value and the enhancement of IT infrastructure for research and development. The technical and business risk associated with the overall vision of this effort brings with it the possibility of significant commercial impact. The innovation is enabled by recent advances in the capacity and functionality of reconfigurable chips which can be used to address near-term business opportunities. It enhances the IT infrastructure by upgrading the existing computing environment with a new type of platform that provides vastly improved performance with lower overall power and space requirements.
