NSF Award
1415803
The broader impacts/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is that the deposition techniques used to deposit the lattice matching materials are scalable in wafer area to 200mm and 300mm wafer processing and are already found in today's CMOS foundries. Both factors, using large area deposition process and leveraging fully depreciated CMOS fabs, lead to significant reduction in overall packaged device cost. In this fashion, these lattice matching materials on Si will result in a new industry standard wafer from a US company supplying globally 200mm and 300mm wafers to light emitting diode and power semiconductor industries.<br/><br/>This Small Business Innovation Research (SBIR) Phase I project is focused on converting the surface of large area silicon wafers into a bulk-like quality Gallium Nitride (GaN). The wafer technology will be used by light emitting diode and power semiconductor manufacturers to grow the brightest and most efficient GaN based devices. The novel technology under this Phase I project is based on depositing a patent pending purely metallic alloy that both grades the lattice constant from Si to GaN and counter balances residual thermal mismatch to maintain a flat wafer. By removing both thermal and lattice mismatch, growth of low defect density GaN is promoted on large area wafers leading to bulk GaN quality material efficiencies.
